FFT IFFT Circuit Using Bit-Reversal Permutation for RAM Efficiency
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Solution Overview
Problem
Existing FFT/IFFT implementations face inefficiencies due to complex control logic and time wastage caused by differing data storage orders in RAM before and after transformation, requiring additional reordering and resource consumption.
Innovation Solution
A circuit and method that maintains consistent data storage orders in RAM by using multiplexers and RAMs to perform iterative butterfly operations with controlled bit reversal and unified read/write addresses, eliminating the need for extra reordering and reducing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If co-located iteration is used to save RAM space, then storage space is reduced, but control complexity increases and time resource is wasted due to different storage orders before and after FFT
Solution Approach 1:
The patent applies bit-reversal permutation to reorder input data before processing. This inversion technique transforms the data arrangement so that after FFT processing, the output data is already in the correct sequential order, eliminating the need for additional reordering operations and simplifying control logic.
Solution Approach 2:
The patent performs preliminary reordering of input data using bit-reversal permutation before the FFT processing stages. This preliminary action ensures that data is arranged in the correct order for processing, and the output is directly in the desired sequential order, avoiding post-processing reordering operations.
2Quantity of substance
If data is read out respectively taking two clocks in co-located iteration, then RAM space is saved, but time consumption increases
Solution Approach 1:
By applying bit-reversal permutation to the input data arrangement, the patent ensures that data elements are positioned such that they can be read and processed in a single clock cycle per element. This inversion of the traditional approach allows simultaneous reading of both inputs for each butterfly operation, eliminating the two-clock reading requirement.
3Device complexity
If iteration form of each level is made the same to reduce control complexity, then control is simplified, but data storage orders before and after FFT remain different requiring reordering
Solution Approach 1:
The patent uses bit-reversal permutation on input data to invert the storage order issue. By preprocessing the data in this inverted manner, the patent achieves uniform iteration forms across all levels while the output naturally appears in sequential order, eliminating the need for additional reordering operations.
4Ease of operation
If multiple RAMs are used to maintain different storage orders, then data organization is improved, but chip area and power consumption increase
Solution Approach 1:
The patent makes a single RAM unit perform multiple functions by implementing bit-reversal permutation logic within the same memory structure. The same RAM is used for both input storage and output storage, with address permutation handling the reordering requirement, eliminating the need for separate RAM units for different data orders.
Solution Approach 2:
The patent merges the reordering function with the existing RAM structure by implementing bit-reversal address generation logic within the same memory unit. This combining of functions allows the system to maintain proper data organization while using a single compact memory structure instead of multiple separate RAMs.
Data Source
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AI summary
A circuit and a method for implementing Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT) are provided. The method includes: determining the number m of iterations, depth d1 of the first and second Random Access Memories (RAMs), depth d2 of a Read Only Memory (ROM); storing the first and second n/2 parts of the input data to be Transformed into the second and first RAMs respectively; performing the iterative butterfly operations m times; in the first iteration, reading the first and second RAMs in a reverse bit order, writing the results of the even-numbered butterfly operations into the first RAM, writing the results of the odd-numbered butterfly operations into the second RAM; during the second to the (m-1)th iterations, reading the first and second RAMs in a normal bit order, wherein the way to write back to the RAM is the same as that of the first time; in the m-th iteration, reading the first and second RAMs in a normal bit order, wherein the location in the RAM to be written back is the same as the location for reading.