Linearized Field Plate Biasing for High-Voltage Gate-Drain Stress
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High voltage semiconductor devices face challenges in managing electrical field stress between the gate and drain, leading to inefficiencies and potential gate overload, especially in off-states due to the large voltage differences.
Innovation Solution
The integration of multiple field plates with a biasing circuit comprising high voltage depletion mode transistors and resistors, where each field plate is independently biased with varying pinch-off voltages based on distance from the gate, effectively relieving electric field stress and creating a flatter field profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the length between gate and drain is increased to handle high voltage electrical fields, then the device can withstand higher voltages in off state, but the device area and complexity increase
Solution Approach 1:
The gate-drain region is segmented into multiple zones by introducing several field plates at different positions. Each field plate is independently biased to create localized field control zones, allowing the device to handle high voltages without requiring a uniformly large gate-drain length, thus reducing overall device complexity while maintaining voltage withstand capability.
Solution Approach 2:
Different regions between gate and drain are provided with different field plate configurations and biasing voltages tailored to local field stress requirements. Areas with higher field stress receive appropriate field plates with specific biasing, while other regions use simpler structures, optimizing the balance between voltage handling and device complexity.
2Loss of energy
If multiple field plates with independent biasing are introduced to linearize the field profile, then leakage current is reduced and efficiency is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The biasing voltages applied to different field plates are specifically optimized to create a linearized field profile across the gate-drain region. By carefully selecting and adjusting these voltage parameters, the patent achieves reduced leakage current and improved efficiency while managing the complexity through parameter optimization rather than structural over-engineering.
3Measurement precision
If field plates are positioned closer to the gate to better control the electrical field, then field control precision is improved, but the risk of gate overload increases
Solution Approach 1:
The biasing circuit is designed with feedback mechanisms that monitor the electrical field conditions and adjust the field plate voltages accordingly. This feedback control allows field plates positioned close to the gate to exert precise field control while automatically preventing conditions that would lead to gate overload, thus resolving the contradiction between control precision and gate safety.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the efficiency of high voltage semiconductor devices by reducing leakage current and maintaining a linearized field profile, improving performance and reliability across on and off states.
Implementation Method 1
each having a different pinch-off voltage based on a distance of the respective field plate from the gate
Data Source
AI summary
An integrated circuit (IC) having a high voltage semiconductor device with a plurality of field plates between the gate and drain. The IC further includes a biasing circuit electrically coupled to each of the plurality of field plates, the biasing circuit including a plurality of high voltage depletion mode transistors, each having a pinch off voltage. The high voltage depletion mode transistors may have different pinch off voltages, and each of the field plates are each independently biased by a different one of the high voltage depletion mode transistors.