Conductive Field Plate Over Gate Structure
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Solution Overview
Problem
In advanced transistor fabrication, the proximity of gate contacts to other conductors leads to unwanted parasitic capacitance and hot carrier injection, which can damage gate dielectric layers and increase the likelihood of short circuits, especially as device dimensions decrease, and there is a need for high voltage semiconductor devices that do not scale with technology.
Innovation Solution
A conductive field plate structure is introduced, including a silicide-blocking layer over a gate spacer, a conductive layer in contact with the silicide-blocking layer, and a field plate contact that electrically couples the conductive layer, preventing penetration through lower layers and reducing parasitic capacitance and hot carrier injection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are reduced to increase devices per chip, then productivity is improved, but parasitic capacitance and hot carrier injection increase causing reliability degradation
Solution Approach 1:
A conductive field plate structure is introduced as an intermediary element between the gate contact and adjacent conductors. This field plate includes a conductive layer over a silicide-blocking layer, which acts as a mediator to control and reduce parasitic capacitance effects while preventing hot carrier injection into the gate dielectric, thereby maintaining reliability as device dimensions are reduced
Solution Approach 2:
The silicide-blocking layer is formed in advance to prevent harmful silicide formation and hot carrier injection before they can damage the gate dielectric. The conductive field plate is also preliminarily configured to establish controlled electric field distribution, creating preliminary protection against parasitic effects before device operation begins
2Area of stationary object
If gate contact proximity to other conductors is maintained for compact design, then device area is reduced, but parasitic capacitance increases degrading device performance
Solution Approach 1:
The conductive field plate serves as an intermediary structure between the gate contact and adjacent conductors, allowing compact device layout while controlling the electric field distribution to minimize parasitic capacitance. The silicide-blocking layer within this structure further mediates the interaction, preventing harmful electrical effects
3Length of moving object
If protective layer dimensions are reduced to match scaled device dimensions, then device scaling is achieved, but short circuit likelihood increases
Solution Approach 1:
The protective field plate structure uses composite material layers - a conductive layer combined with a silicide-blocking layer. This composite structure provides both the necessary electrical functionality and protective properties, maintaining reliability even as overall dimensions are reduced for device scaling
Solution Approach 2:
The silicide-blocking layer provides localized protection at critical interfaces where hot carrier injection and silicide formation could cause failures. This local quality enhancement ensures reliability at specific vulnerability points without requiring proportional increases in overall protective layer dimensions
Data Source
AI summary
Embodiments of the disclosure provide an integrated circuit device and related methods. The disclosure may provide a transistor device, including: a gate structure; a drain extension region extending laterally from partially under the gate structure to a drain region; and a gate spacer located over the drain extension region. A silicide-blocking layer is over and in contact with the gate spacer. The silicide-blocking layer has a first end over the gate structure and a second, opposing end over the drain extension region. The structure also provides a conductive field plate, including a conductive layer over and in contact with the silicide-blocking layer. A field plate contact is formed on the conductive field plate.