FIFO Buffer Latency Estimation Using Pattern Detection
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Solution Overview
Problem
Existing phase compensation buffers in communication links cannot accurately determine latency to a fraction of a cycle due to rapidly changing write and read pointers, limiting their effectiveness in managing communication link performance.
Innovation Solution
A circuit and method that uses detectors to identify patterns in data values written to and read from a FIFO buffer, with a counter counting active transitions of a sample clock signal to estimate latency, providing a more precise measurement of latency through the buffer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If write and read pointers are used to determine latency in a phase compensation buffer, then the latency can be determined at the cycle level, but the measurement precision is insufficient to achieve fraction-of-a-cycle accuracy because the pointers change too quickly
Solution Approach 1:
The patent introduces an intermediary sampling mechanism that captures pointer positions at discrete intervals. Instead of directly measuring the rapidly changing pointers, the invention uses a sampler to capture their positions at specific moments, converting the continuous high-speed pointer changes into discrete, measurable samples that can be accurately recorded and processed to determine fractional cycle latency.
Solution Approach 2:
The invention creates copies of the pointer positions at each sampling instant. By capturing and storing multiple copies of pointer positions over time, the system can analyze the relationship between write and read pointer copies to calculate latency with fractional cycle precision, rather than relying on a single direct pointer reading.
2Measurement precision
If the sampling period is reduced to improve latency estimation accuracy, then the measurement precision increases, but the device complexity increases due to the need for higher frequency sampling
Solution Approach 1:
The patent applies partial action by sampling at a moderate frequency that captures sufficient information for accurate latency estimation without requiring excessively high sampling rates. The invention demonstrates that complete continuous sampling is not necessary - strategic partial sampling at optimized intervals achieves the required precision while maintaining manageable system complexity.
Solution Approach 2:
The invention optimizes the sampling period parameter to achieve the best balance between measurement accuracy and system complexity. By carefully selecting and adjusting the sampling period parameter, the system achieves fraction-of-a-cycle latency measurement precision without requiring prohibitively high sampling frequencies that would increase device complexity.
Data Source
AI summary
Circuits and methods are provided for estimating a latency through a FIFO buffer. A first detector detects first instances of a pattern in first data values serially written to a write port of the FIFO buffer. A second detector detects second instances of the pattern in second data values serially read from a read port of the FIFO buffer. The second data values are the first data values delayed by the latency through the FIFO buffer. A counter counts a count of active transitions of a sample clock signal. The counter starts on each detected first instance and stops on each detected second instances. The count provides an estimate of the latency of the FIFO buffer.