Customizable Filler Cell Placement Algorithm for IC Layout Optimization
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Solution Overview
Problem
The random distribution and limited availability of customizable filler cells in integrated circuit physical design layouts hinder effective circuit modifications, as they are often clustered near the perimeter and not evenly distributed, restricting the ability to implement necessary changes.
Innovation Solution
A method involving the adjustment of logic cell positions to combine smaller filler cells into larger customizable filler cells, optimizing their placement and distribution across the circuit layout using a filler cell placement algorithm within electronic design automation tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If filler cells are added to fill empty spaces in circuit rows and columns, then the empty spaces are filled and design completeness is improved, but the locations and distribution of customizable filler cells become random and uncontrolled
Solution Approach 1:
The patent reserves specific regions during the logic synthesis stage before final placement, designating these as potential customizable filler cell locations. By performing this reservation action preliminarily, the system ensures that customizable filler cells will be available in strategic locations without interfering with the random filling of smaller empty spaces that occurs naturally during placement.
Solution Approach 2:
The patent segments the circuit layout into different types of spaces: small empty spaces that are filled with standard filler cells, and larger reserved regions that are designated for customizable filler cells. This segmentation allows the system to address different filling needs separately, ensuring both complete coverage and controlled distribution of customizable cells.
2Adaptability or versatility
If logic cells are moved to combine filler cells into larger customizable filler cells, then the size and usability of filler cells is improved, but the placement complexity and processing time increases
Solution Approach 1:
The patent applies different filling strategies to different regions of the circuit layout. Standard filler cells are used to fill small random empty spaces, while reserved regions with sufficient area are designated for customizable filler cells. This local differentiation allows the system to optimize for customizability only where appropriate, without unnecessarily complicating the overall placement process.
3Adaptability or versatility
If customizable filler cells are distributed evenly throughout the circuit layout, then the ability to implement circuit modifications is improved, but the random distribution resulting from placement algorithms prevents controlled placement
Solution Approach 1:
The system performs preliminary reservation of regions during logic synthesis to guarantee customizable filler cell locations before the placement algorithm executes. This preliminary action ensures that even though the placement algorithm operates randomly, customizable filler cells will still be available in strategically important regions throughout the layout.
Data Source
AI summary
A system and method for optimizing customizable filler cells in an integrated circuit physical design process. In particular, a filler cell placement algorithm of the present disclosure is utilized in the method to optimize the customizable filler cells in a circuit layout. The filler cell placement algorithm performs the operation of selecting a starting point within a given circuit layout, selecting a direction in which the position of logic cells is adjusted, adjusting the position of logic cells and, thereby, combining filler cells in order to increase the accumulated area thereof; suspending the adjustment operation when a customizable filler cell is formed; and resuming the adjustment operation from the point of the newly formed customizable filler cell. Additionally, a method of optimizing the locations, number, and distribution of the customizable filler cells in an integrated circuit design by use of the filler cell placement algorithm is provided.