Filler Cell Layout for Shared FinFET Threshold Voltage Regions
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Solution Overview
Problem
The transition from planar MOSFETs to FinFETs in semiconductor technology has resulted in poor area utilization and increased costs for logic circuits due to the incompatibility of existing logic sharing technologies.
Innovation Solution
The introduction of a filler cell with two dummy polysilicon layers and threshold voltage layers, allowing transistor cells to share dopants and reduce area, coupled with a guard ring structure for protection, enhances area utilization and reduces manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional logic sharing technology is used for FinFETs, then the design process is simplified, but the area utilization becomes poor and manufacturing cost increases
Solution Approach 1:
Multiple transistor cells share a common dummy polysilicon layer, merging what would traditionally be separate structures into a shared resource that benefits multiple cells simultaneously
Solution Approach 2:
The dummy polysilicon layer serves multiple functions: it provides threshold voltage control for adjacent transistor cells, acts as a shared structural element, and enables area reduction while maintaining device functionality
2Area of stationary object
If transistor cells are arranged closely to improve area utilization, then the logic circuit area decreases, but the manufacturing complexity increases
Solution Approach 1:
The logic circuit is divided into modular transistor cells that can be systematically arranged and shared, breaking down the complex design into repeatable units
Solution Approach 2:
The design transitions to utilizing vertical stacking and three-dimensional arrangements of transistor cells, moving beyond traditional planar layouts to achieve higher density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient design of semiconductor devices with specific functions at lower costs and higher area utilization, facilitating the development of larger logic circuits with complex functions.
Implementation Method 1
The first threshold voltage layer has a dopant with a single concentration, and the first threshold voltage layer and each of the two second threshold voltage layers have dopants with different polarities
Data Source
AI summary
A filler cell, a semiconductor device, and a logic circuit are provided. The filler cell includes two dummy polysilicon layers and a threshold voltage layer. The dummy polysilicon layers are arranged at intervals in a first direction. The threshold voltage layer is below the dummy polysilicon layers, and the two opposite sides of the threshold voltage layer in the first direction extend in a second direction and are respectively aligned with center points of the dummy polysilicon layers. The two opposite sides of the threshold voltage layer in the second direction are respectively aligned with the two opposite sides of each of the dummy polysilicon layers in the second direction. The first direction is perpendicular to the second direction. The semiconductor device includes a plurality of filler cells, at least one transistor cell, and another two threshold voltage layers. The logic circuit includes a plurality of semiconductor devices.