Filler Cells for Stress Mitigation in IC Layout
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Solution Overview
Problem
Integrated circuit performance is hindered by mechanical stress from differential expansion and contraction of materials during fabrication, particularly due to shallow trench isolation regions, which affects transistor performance and requires manual layout adjustments compromising other performance measures.
Innovation Solution
A system and method for improving integrated circuit layouts by inserting filler cells into gaps between circuit layout cells, selected from a database based on desired performance parameters, to alleviate stress effects and enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation regions are used to electrically isolate active regions, then electrical isolation is achieved, but compressive stress is introduced that degrades transistor mobility and performance
Solution Approach 1:
The patent introduces filler cells as intermediary elements between adjacent circuit cells. These filler cells contain dummy diffusion regions that act as stress-absorbing intermediaries, reducing the compressive stress transmitted from STI regions to the transistor channels. The dummy diffusions serve as a buffer zone that mediates the stress interaction between isolation structures and active devices.
Solution Approach 2:
The patent modifies the physical and material parameters of the layout structure by introducing filler cells with specific properties (dummy diffusion regions, polysilicon lines, N-well boundary shifts). These parameter changes in the layout configuration alter the stress distribution pattern, transforming the harmful compressive stress into a more favorable stress profile that preserves transistor mobility.
2Reliability
If transistor size is increased to compensate for stress-induced performance degradation, then transistor strength is improved, but power consumption increases
Solution Approach 1:
The patent converts the harmful compressive stress from STI regions into a beneficial layout feature by strategically placing filler cells. Instead of viewing stress as purely detrimental, the invention utilizes stress-aware layout techniques where filler cells are positioned to create favorable stress patterns that enhance transistor performance without requiring size increases. This transforms the stress problem into a design opportunity.
Solution Approach 2:
The patent applies local quality optimization by introducing filler cells with specific properties at strategic locations between circuit cells. Rather than uniformly increasing all transistor sizes, the invention applies localized stress management techniques where filler cells are inserted only where needed to protect specific transistors from stress-induced degradation, thereby maintaining power efficiency while improving local transistor strength.
3Measurement precision
If manual layout revision is performed to account for stress effects, then circuit performance prediction accuracy is improved, but design complexity and time increase
Solution Approach 1:
The patent applies preliminary action by inserting filler cells during the automated place-and-route process, before final layout optimization. The stress management measures are taken in advance during the placement stage, allowing subsequent routing and optimization to proceed without needing manual revisions. This preliminary stress-aware placement integrates stress considerations into the automated flow, maintaining accuracy while reducing complexity.
Solution Approach 2:
The patent enables the layout system to self-adjust for stress effects through automated filler cell insertion. The place-and-route tool automatically identifies where filler cells are needed and inserts them without requiring manual intervention. This self-service approach allows the design tool to handle stress compensation autonomously, improving prediction accuracy while avoiding the complexity of manual layout revision processes.
4Manufacturing precision
If filler cells are inserted to reduce stress effects, then transistor mobility is improved, but layout density decreases
Solution Approach 1:
The patent applies partial action by inserting filler cells only in specific locations where stress effects are most problematic, rather than uniformly across the entire layout. The automated system identifies critical areas where filler cells provide the most benefit and inserts them selectively. This partial approach maintains layout density by avoiding unnecessary filler cells in regions where stress management is less critical.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for optimized transistor performance by reducing compressive stress, thereby enhancing switching speed and ion mobility, while maintaining power consumption and layout integrity, through the strategic placement and design of filler cells.
Implementation Method 1
semiconductor materials such as silicon and germanium exhibit the piezoelectric effect (mechanical stress-induced changes in electrical resistance)
Implementation Method 2
During the subsequent wafer cooling, oxides tend to shrink less than the surrounding silicon, and therefore develop a state of compressive stress laterally on the silicon regions
Data Source
AI summary
A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.