Gate-Aligned Fin Cut Layout for Dense FinFET Isolation
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in maintaining mobility improvement and short channel control as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, where lithographic processes face constraints due to the trade-off between feature dimension and spacing, leading to over-dimensioning and reduced transistor density.
Innovation Solution
Implementing a gate aligned fin cut isolation technique where fins are cut after gate patterning, allowing self-aligned isolation with gate electrodes, reducing the need for multiple dummy gates and enabling higher transistor density by aligning fin isolation perfectly on-pitch with gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern semiconductor features, then feature patterning can be achieved, but the spacing between features must be increased leading to over-dimensioning and reduced transistor density
Solution Approach 1:
The fin cut is performed preliminarily before gate patterning, creating pre-defined fin segments with precise spacing. This preliminary structuring allows subsequent gate electrodes to be self-aligned to the fin segments, eliminating the need for additional spacing that would otherwise be required for alignment, thereby resolving the contradiction between feature dimension precision and spacing requirements
Solution Approach 2:
The gate electrodes serve themselves by being automatically aligned to the pre-formed fin segments through the self-aligned fabrication process. This self-alignment mechanism eliminates the need for separate alignment steps and dummy gates, allowing features to be patterned at their minimum required spacing without over-dimensioning, thus resolving the spacing versus precision contradiction
2Manufacturing precision
If multiple dummy gates are used to maintain alignment, then alignment accuracy is improved, but transistor density is reduced due to increased device footprint
Solution Approach 1:
The fabrication process makes the fin segments self-align to the gate electrodes through self-aligned fabrication techniques. The gate electrodes automatically position themselves relative to the pre-formed fin segments without requiring dummy gates for alignment, thereby maintaining high alignment accuracy while eliminating the space-consuming dummy structures, thus resolving the contradiction between alignment precision and transistor density
Solution Approach 2:
The dummy gates, which are unnecessary structural elements used for alignment in conventional processes, are completely removed from the fabrication sequence. By extracting and eliminating these redundant components, the invention achieves alignment accuracy through the self-aligned process while maximizing transistor density by removing the space occupation of dummy gates
Data Source
AI summary
Gate aligned fin cut for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a first fin segment having a fin end, and a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment. A first gate structure is over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment. A second gate structure is over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment. An isolation structure is laterally between the fin end of the first fin segment and the fin end of the second fin segment.