Fin-Shaped Semiconductor Structure Etching Endpoint Control
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Solution Overview
Problem
Conventional methods struggle to precisely control the thickness and shape of vertical fin-shaped semiconductor structures during etching due to limitations in end point detection for non-planar surfaces, hindering the fabrication of advanced FinFETs with features below 100 nm.
Innovation Solution
A method involving a semiconductor substrate with a dielectric layer and a mask layer, where an etching process simultaneously removes portions of the mask layer, dielectric layer, and semiconductor island, allowing for pre-set etching rates and endpoint control, replacing conventional detection methods like IEP and OES.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional interferometer end point (IEP) detection or optical emission spectroscopy (OES) detection is used during etching, then the etching process can be monitored, but the thickness and shape of the vertical fin-shaped semiconductor structure cannot be precisely controlled due to the non-planar surface configuration
Solution Approach 1:
The etching process is divided into multiple stages with different selectivity ratios. The mask layer is etched with a first selectivity ratio, the dielectric layer with a second selectivity ratio, and the semiconductor island with a third selectivity ratio. This segmentation allows independent control of each layer's removal rate, enabling precise thickness and shape control of the fin structure despite the non-planar surface configuration that renders conventional IEP or OES detection ineffective.
2Productivity
If the gate length is scaled below 100 nm to meet high density and performance demands, then device performance improves, but short channel effects such as excessive leakage between source and drain become increasingly difficult to overcome
Solution Approach 1:
The invention transitions from conventional planar MOSFETs to FinFETs by introducing a vertical dimension. The semiconductor island is etched to form a vertical fin-shaped structure with curved top surfaces, transforming the device architecture from two-dimensional planar to three-dimensional vertical. This dimensional change provides better gate control over the channel, suppressing short channel effects and enabling continued scaling below 100 nm while maintaining reliability.
3Manufacturing precision
If simultaneous etching of mask layer, dielectric layer, and semiconductor island is performed with different selectivity ratios, then precise control of fin structure thickness and shape is achieved, but the etching process complexity increases
Solution Approach 1:
The etching process utilizes controlled changes in selectivity ratios between different material layers. By adjusting etching parameters such as gas composition, power, and pressure, the process achieves first, second, and third selectivity ratios for the mask layer, dielectric layer, and semiconductor island respectively. This parameter control enables precise fin structure formation despite the increased process complexity, as the selective etching rates allow independent thickness control of each layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise control of etching endpoint, ensuring consistent and controlled formation of fin-shaped semiconductor structures with curved top surfaces and varying thicknesses, facilitating the fabrication of high-performance FinFETs.
Implementation Method 1
performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening
Data Source
AI summary
A method for fabricating a fin-shaped semiconductor structure is provided, including: providing a semiconductor substrate with a semiconductor island and a dielectric layer formed thereover; forming a mask layer over the semiconductor island and the dielectric layer; forming an opening in the mask layer, exposing a top surface of the semiconductor island and portions of the dielectric layer adjacent to the semiconductor island; performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening; and removing the mask layer and the dielectric layer, leaving an etched semiconductor island with curved top surfaces and various thicknesses over the semiconductor substrate.