Fin Gate Semiconductor Device With Compressive Stress Active Pillar
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Solution Overview
Problem
Current electronic charge-controlled devices face limitations in developing next-generation memory devices with high capacity, ultra-high speed, and ultra-low power, necessitating the development of new functional memory devices, particularly variable resistive memory devices that require improved integration density and high operation current for maintaining resistance characteristics.
Innovation Solution
A semiconductor device with a fin gate structure is developed, featuring an active pillar with a semiconductor layer having a smaller lattice constant than the surrounding region, causing compressive stress at the junction interface, which enhances carrier mobility and current drivability in PMOS transistors, and is integrated into a variable resistive memory device with a gate insulating layer and a fin gate extending to surround the active pillar.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a three-dimensional transistor structure with surrounding gate or fin gate is employed to improve integration density, then the number of memory cells per unit area increases, but the operation current requirement increases to maintain high resistance variable characteristics
Solution Approach 1:
The patent applies local quality by creating different stress conditions in different regions of the active pillar. The inner region is subjected to compressive stress while the outer region experiences tensile stress, optimizing carrier mobility locally in each region to reduce overall operation current requirements while maintaining high integration density through the 3D fin gate structure
Solution Approach 2:
The patent changes the stress parameter in the active pillar by introducing an inner region with different stress characteristics (compressive) compared to the outer region (tensile). This parameter change optimizes the electrical characteristics of the transistor, enabling lower operation current while maintaining the high integration density provided by the surrounding gate structure
2Reliability
If compressive stress is applied to the active pillar to enhance carrier mobility in PMOS transistors, then current drivability improves, but manufacturing complexity increases due to lattice constant differences between inner and outer regions
Solution Approach 1:
The patent segments the active pillar into an inner region and an outer region with different materials and stress characteristics. This segmentation allows independent optimization of each region's properties, achieving enhanced carrier mobility through compressive stress in the inner region while managing manufacturing complexity through systematic material selection and structured fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The fin gate structure improves carrier mobility and current drivability of PMOS transistors, enabling enhanced operation characteristics and integration density in variable resistive memory devices, addressing the need for high-capacity and low-power memory solutions.
Implementation Method 1
the active pillar is formed in such a manner that compressive stress is caused in a junction interface between the inner region and the outer region
Data Source
AI summary
A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same are provided. The semiconductor device includes an active pillar formed on a semiconductor substrate, and including a first region and a second region surrounding at least one surface of the first region, and a fin gate extending to overlap an upper surface and a lateral surface of the active pillar. The first region of the active pillar is formed of a semiconductor layer having a lattice constant smaller than that of the second region of the active pillar.