Fin Index Modeling for Semiconductor Mandrel Tolerance
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in controlling the variability of critical dimensions and pitch spacing between neighboring features in three-dimensional structures like FinFETs, leading to irregular fin spacing that affects transistor performance and increases production costs.
Innovation Solution
A method and system for modeling mandrel tolerance in semiconductor device design using a multiple patterning process design kit (PDK) to identify and compensate for mandrel mismatches by grouping fins based on their spacings, determining device parameters, and modifying the design to optimize power, performance, and area (PPA) through systematic offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple patterning process is used to manufacture FinFETs, then transistor density and integration are improved, but mandrel tolerance variability causes irregular fin spacing that degrades transistor performance
Solution Approach 1:
The patent applies preliminary action by performing mandrel tolerance modeling and fin grouping analysis during the design phase before manufacturing. The system pre-identifies fins with similar spacing characteristics and groups them together, allowing designers to compensate for expected tolerances in advance rather than dealing with variability after fabrication.
Solution Approach 2:
The patent changes parameters by introducing deterministic offsets to device parameters (such as width, length, or doping) based on the grouped fin configurations. This parameter adjustment compensates for the irregular fin spacing caused by mandrel tolerance, maintaining transistor performance despite manufacturing variability.
2Device complexity
If traditional parasitic extraction methods are used without mandrel tolerance modeling, then design flow simplicity is maintained, but accuracy in predicting actual hardware behavior is insufficient
Solution Approach 1:
The patent segments the parasitic extraction process by introducing a distinct mandrel tolerance modeling step that operates independently from traditional extraction. Fin indices are generated and fins are grouped based on spacing characteristics, creating modular components that can be processed separately and then integrated, improving accuracy without completely redesigning the flow.
Solution Approach 2:
The patent introduces fin indices and grouping information as intermediary data structures between the layout and parasitic extraction stages. These intermediaries carry information about mandrel tolerance effects and fin spacing variations, enabling accurate modeling without requiring complete redesign of the existing extraction infrastructure.
3Measurement precision
If detailed simulations are run to account for local variability, then circuit performance accuracy is improved, but simulation time increases significantly
Solution Approach 1:
The patent performs preliminary grouping of fins by spacing characteristics before detailed simulation. By pre-organizing fins into groups with similar tolerance profiles, the system reduces the complexity of subsequent simulations and allows for more efficient analysis while maintaining accuracy.
Solution Approach 2:
The patent applies local quality by treating different fin groups with appropriate levels of simulation detail based on their specific spacing characteristics. Fins that are grouped together due to similar tolerance behavior can be simulated with standardized models, while only critical individual fins require detailed analysis, reducing overall simulation time.
Data Source
AI summary
A computer-implemented method for modeling mandrel tolerance in a design of semiconductor device. The method includes receiving a multiple patterning (MPT) process design kit (PDK) for the semiconductor device. The PDK includes design parameters of a plurality of transistors that form at least part of the semiconductor device and a plurality of fins associated with each of the plurality of transistors. The method includes generating a fin index identifying each of the plurality of fins and grouping the fin indexes of the plurality of fins into two or more groups based on a type of fin. The method further includes identifying a mandrel mismatch in response to determining that a first fin index associated with a first transistor belongs to a group that is different from a second fin index associated with a second transistor. The method also includes determining a device parameter based on the mandrel mismatch identified.