Fin Isolation Via Layout for Dense IC Backside Routing
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Solution Overview
Problem
As integrated circuits scale downward in size, forming semiconductor devices with vias and fin isolation structures becomes increasingly challenging due to limited space and densely packed transistors, making it difficult to efficiently use the available space for device packing and routing.
Innovation Solution
The integration of conductive vias through fin isolation structures, which share the same location as the fin isolation structures, allowing for wider vias that extend vertically and provide electrical connections between frontside and backside features, freeing up space for more efficient device packing and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are packed more densely to reduce device size, then device packing efficiency is improved, but via formation becomes more challenging
Solution Approach 1:
The patent combines the fin isolation structure and conductive via into a single integrated structure. The via is formed through the fin isolation structure, merging two previously separate fabrication processes into one unified approach, thereby simplifying manufacturing while maintaining high device packing density
Solution Approach 2:
The fin isolation structure serves multiple functions: it provides electrical isolation between fins and simultaneously houses the conductive via for vertical interconnect. This multi-functionality reduces the need for separate via formation steps, easing manufacturing complexity while supporting dense device packing
2Area of stationary object
If device spacing is reduced at the device layer, then integrated circuit size is reduced, but space for routing becomes limited
Solution Approach 1:
The patent transitions routing from a two-dimensional planar approach to a three-dimensional approach by forming vias that extend vertically through the fin isolation structure. This vertical interconnect provides additional routing dimension, enabling signal transmission without requiring additional lateral space, thus maintaining compact integrated circuit area while preserving routing capability
3Productivity
If conductive vias are formed through fin isolation structures, then space efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The conductive via is formed during the fin isolation structure fabrication process itself, rather than as a subsequent separate step. The via precursor structure is prepared alongside the fin isolation structure, and the conductive material is deposited in the same process sequence, thereby achieving high space utilization without adding significant manufacturing complexity
Data Source
AI summary
Techniques are provided herein to form an integrated circuit having a conductive via extending through a fin isolation structure. Transistors each include semiconductor material extending colinearly in a first direction between source and drain regions, and gate structures extending in a second direction around the semiconductor material of each transistor. A fin isolation structure may extend along the second direction between the transistor s to provide electrical isolation between the transistors. The fin isolation structure may include one or more dielectric materials that are deposited within a trench extending between the transistors. A conductive via extends through the core of the fin isolation structure to provide electrical connection between frontside features and backside features of the integrated circuit. In this way, the conductive via shares the same location as the fin isolation structure which provides efficient use of the limited space on a given die.