Fin Memory Cell With Doped Cap Layer To Suppress Leakage
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Solution Overview
Problem
Current memory cell technologies face challenges in increasing storage capacity while maintaining performance and reliability, particularly due to current leakage issues in shrinking devices, which are exacerbated by high electric fields and complex, expensive manufacturing processes.
Innovation Solution
A memory cell design featuring a doped region and doped cap layer on a fin structure with a charge trapping mechanism, where the doped regions have a conductive type complementary to the channel, reducing current leakage and enabling simpler, cost-effective manufacturing through a surface treatment and trimming process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are shrunk to increase storage capacity, then integration density is improved, but current leakage increases and electrical performance deteriorates
Solution Approach 1:
The patent applies local quality by creating a doped cap layer with complementary conductivity type specifically at the top corner regions of the fin structure, while leaving other regions with their original conductivity. This localized doping approach targets the specific areas where current leakage occurs (top corners) without altering the overall device architecture, thereby improving electrical performance in critical regions while maintaining the shrunk form factor for high integration density.
2Reliability
If double gate or tri-gate memory cells are used to improve electrical performance, then device speed and functions are improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies preliminary action by performing a surface treatment process (such as ion implantation or plasma treatment) during the standard CMOS fabrication sequence to modify the conductivity of the cap layer at the fin top corners. This preliminary modification is integrated into the existing manufacturing flow before final device assembly, avoiding the need for complex additional processing steps required by double gate or tri-gate structures, thereby achieving improved electrical performance with minimal increase in manufacturing complexity.
3Speed
If tri-gate memory cells are used to improve electrical performance, then device speed is improved, but current leakage occurs at corners and production yield decreases
Solution Approach 1:
The patent converts the harmful effect of high electric fields at the fin top corners (which cause current leakage) into a beneficial feature by deliberately doping these regions with complementary conductivity type. The same geometric feature (sharp corners) that causes the problem is transformed into a solution by adding controlled doping, thereby eliminating current leakage while preserving the high-speed performance enabled by the vertical fin structure.
4Quantity of substance
If memory cell size is reduced to increase integration, then storage capacity is improved, but step height between fin structure and isolation structure increases
Solution Approach 1:
The patent applies parameter changes by modifying the conductivity parameter of the cap layer at the fin top corners through surface treatment. This changes the electrical parameters (conductivity type) to suppress current leakage, and indirectly affects the physical parameters by reducing the effective step height through electrical field modulation, thereby achieving both high integration density and reduced step height effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design suppresses current leakage, improves electrical performance, and increases integration density by minimizing the step height and size of memory cells, while maintaining reliability and reducing production costs.
Implementation Method 1
a doped region with a conductive type complementary to that of the channel between the source/drain regions is formed in the top corner of the fin structure
Implementation Method 2
a charge trapping structure is formed between the gate and the fin structure
Data Source
AI summary
In a method for manufacturing a memory cell, a substrate is provided. A doped region with a first conductive type is formed in the substrate near a surface of the substrate. A portion of the substrate is removed to define a plurality of fin structures in the substrate. A plurality of isolation structures is formed among the fin structures. A surface of the isolation structures is lower than a surface of the fin structures. A gate structure is formed over the substrate and straddles the fin structure. The gate structure includes a gate straddling the fin structure and a charge storage structure located between the fin structure and the gate. A source/drain region is formed with a second conductive type in the fin structure exposed by the gate structure, and the first conductive type is different from the second conductive type.