Fin Oxide Isolation for Stacked Transistor Density
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Solution Overview
Problem
Current methods for manufacturing stacked transistors face challenges such as defects due to lattice constant differences between silicon and silicon germanium layers, and high costs associated with using silicon on insulator wafers, which limit the density and performance of transistors in mobile electronic devices.
Innovation Solution
The use of localized oxide formation techniques, including catalytic oxide and oxygen implant methods, to create oxide layers between stacked channels within fins, allowing for electrical separation and reduced parasitic capacitance, thereby enhancing transistor density and performance without the need for additional doping or expensive substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon on insulator wafers are used to manufacture stacked transistors, then electrical isolation between channels is achieved, but manufacturing cost increases significantly
Solution Approach 1:
The patent applies local oxidation to specific regions within the fin structure to create oxide layers only where electrical isolation is needed, rather than using expensive silicon on insulator wafers for the entire substrate. This localized approach achieves the required electrical isolation between channels while maintaining cost-effectiveness by treating only specific areas with oxidation processes.
2Productivity
If silicon and silicon germanium layers are stacked to increase transistor density, then device performance improves, but defects occur due to lattice constant differences
Solution Approach 1:
The patent employs strain engineering by controlling the thickness, composition, and stacking sequence of silicon and silicon germanium layers to manage lattice mismatch. By adjusting these parameters, the patent reduces defect formation while maintaining high transistor density through vertical stacking of channels.
3Speed
If additional doping is performed to enhance transistor performance, then carrier mobility improves, but dopant variation increases
Solution Approach 1:
The patent replaces traditional doping mechanisms with alternative approaches such as material composition control and strain engineering. By using epitaxial growth techniques to precisely control material composition and applying mechanical strain through layered structures, the patent achieves enhanced carrier mobility without the variability introduced by additional doping processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases transistor density and performance by electrically isolating channels, reducing parasitic capacitance, and eliminating the need for costly substrates, while maintaining or improving carrier mobility and reducing dopant variation.
Implementation Method 1
annealing the deposited catalytic oxidant material to form an oxide in at least a portion of a volume of the fin
Implementation Method 2
applying a plasma implant process or a beam-line implant process to a second portion of the fin to deposit oxygen ions into a third portion of the fin
Data Source
AI summary
Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.