Fin-Type Semiconductor Device With Blocking Pattern For Short Channel Effect
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing density and controlling current effectively without scaling gate length, while also suppressing the short channel effect in multi-gate transistors.
Innovation Solution
A method of fabricating semiconductor devices involves forming a fin-type active pattern with a gate pattern that intersects it, using a blocking pattern to expose side surfaces, and selectively growing an epitaxial layer on these surfaces to form source/drain regions, allowing for increased current control and density without scaling gate length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are adopted to increase density, then transistor density is improved, but short channel effect worsens
Solution Approach 1:
The patent implements multi-gate transistors with three-dimensional (3D) channels that extend vertically from the substrate, transitioning from planar 2D channels to 3D structures. This dimensional change allows additional gate contacts to control the channel from multiple directions (top, front, back), achieving both higher density and improved short channel effect suppression through enhanced electrostatic control in the vertical dimension
2Reliability
If gate length is increased to suppress short channel effect, then short channel effect is improved, but current control capability worsens
Solution Approach 1:
The patent uses vertical 3D channels extending from the substrate with gates positioned at multiple locations along the channel length (including top, front, and back gates). This dimensional transition allows the channel length to be extended vertically without increasing the planar gate length, maintaining current control while achieving better short channel effect suppression through distributed gate control in the vertical dimension
Solution Approach 2:
The patent divides the gate control into multiple segmented gates positioned at different locations along the 3D channel (first gate, second gate, third gate). This segmentation allows independent control of different channel regions, enabling effective short channel effect suppression while maintaining optimal current control capability through distributed gate electrodes rather than a single continuous gate
3Ease of manufacture
If conventional fabrication methods are used, then manufacturing process is simple, but manufacturing precision worsens
Solution Approach 1:
The patent forms blocking patterns on the fin-type active pattern before forming the gate pattern, creating predetermined regions that control subsequent material deposition and etching processes. This preliminary blocking structure enables precise alignment of source/drain regions with the fin structure and ensures accurate positioning of multiple gate electrodes relative to each other and to the fin, achieving high manufacturing precision through pre-established alignment references
Solution Approach 2:
The patent applies blocking patterns selectively to specific portions of the fin-type active pattern (first blocking pattern on first portion, second blocking pattern on second portion). This localized blocking approach allows different regions to be processed differently, enabling precise control over where source/drain materials are deposited and where gates are formed, achieving high manufacturing precision through spatially differentiated processing conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective suppression of the short channel effect and allows for increased transistor density and current control, enhancing the performance of semiconductor devices.
Implementation Method 1
selectively growing an epitaxial layer on the side surfaces of the second region of the fin-type active pattern
Data Source
AI summary
A method for fabricating a semiconductor device is provided. The method includes forming a gate pattern which intersects a fin-type active pattern protruding upward from a device isolation layer. A first blocking pattern is formed on a portion of the fin-type active pattern, which does not overlap the gate pattern. Side surfaces of the portion of the fin-type active pattern are exposed. A semiconductor pattern is formed on the exposed side surfaces of the portion of the fin-type active pattern after the forming of the first blocking pattern.