Fin-Type Selector MTP RRAM for CMOS Integration
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Solution Overview
Problem
The existing process for forming flash memory is complex and costly, and there is a need for a simplified design and process for multi-time programmable (MTP) non-volatile memory (NVM) devices with improved performance and lower fabrication costs.
Innovation Solution
The development of CMOS logic-compatible high-density MTP RRAM devices using fin-type based selectors and storage elements, where a substrate is prepared with regions for MTP RRAM cells and logic transistors, and a fin-type based selector is coupled in series with the storage element to form a compact and efficient memory cell structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flash memory process is used, then non-volatile memory storage is achieved, but process complexity and fabrication cost increase
Solution Approach 1:
The patent changes the fundamental storage mechanism from flash memory's charge trapping in oxide layers to resistive switching in metal-oxide layers. This parameter change in the storage mechanism allows for simpler processing steps while maintaining non-volatile memory functionality, directly resolving the contradiction between reliability and process complexity
Solution Approach 2:
The patent extracts and removes the complex flash memory formation processes (tunnel oxide formation, charge trap layer engineering, complex programming/erasing sequences) and replaces them with a simplified resistive memory approach using metal-oxide layers and electrochemical switching, thereby reducing fabrication complexity while preserving non-volatile storage capability
2Reliability
If flash memory process is used, then non-volatile memory storage is achieved, but fabrication cost increases
Solution Approach 1:
The patent changes the material stack from silicon-oxide-based flash memory to metal-oxide-based resistive memory, using materials like HfO2, Ta2O5, or TiO2 that can be deposited using standard atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques. This parameter change in material selection and deposition methodology reduces fabrication cost while maintaining non-volatile storage reliability
Solution Approach 2:
The patent employs metal-oxide layers that can be formed using relatively inexpensive and well-established semiconductor manufacturing techniques compared to the specialized processes required for flash memory. The resistive switching mechanism also eliminates the need for complex programming and erasing operations, reducing overall fabrication and operational costs
3Reliability
If fin-type based selector is used, then on/off current ratio is improved, but device structure complexity increases
Solution Approach 1:
The patent implements a nested structure where the fin-type selector is vertically integrated with the metal-oxide resistive memory stack. The selector fin structure is formed first, then the metal-oxide layers are deposited conformally around and on the fin, creating a three-dimensional nested architecture. This nesting approach improves the on/off current ratio by providing better current confinement while managing structural complexity through vertical integration rather than lateral expansion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of high-density, cost-effective MTP RRAM devices with improved performance, enabling efficient integration with CMOS logic processing and reducing the complexity and cost of fabrication, while also enhancing the on/off current ratio through band-gap engineering.
Implementation Method 1
enhancing the on/off current ratio through band-gap engineering
Data Source
AI summary
Multi-time programmable (MTP) random access memory (RRAM) devices and methods for forming a MTP RRAM device are disclosed. The method includes providing a substrate. The substrate is prepared with at least a first region for accommodating one or more multi-programmable based resistive random access memory (RRAM) cell. A fin-type based selector is provided over the substrate in the first region. A storage element of the RRAM cell is formed over the fin-type based selector. The fin-type based selector is coupled in series with the storage element of the RRAM cell.