Fin-Type Stacked Memory With Common Semiconductor Layer
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Solution Overview
Problem
Conventional three-dimensional stacked layer type semiconductor memory devices face challenges in achieving high memory cell integration and accurate reading/writing/erasing due to insufficient cut-off characteristics of drain-side select transistors, leading to unnecessary current leakage between memory strings.
Innovation Solution
A fin-type stacked layer structure with a common semiconductor layer connecting the drain ends of multiple memory strings and layer select transistors, where the edge of the insulating layer is positioned to prevent current leakage, allowing for precise selection and operation of individual memory strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a common semiconductor layer is used to connect drain ends of stacked active areas and provide drain-side select transistors, then the degree of memory cell integration is improved, but sufficient cut-off characteristics for the drain-side select transistors cannot be obtained
Solution Approach 1:
The common semiconductor layer is divided into multiple regions with different impurity concentrations. Specifically, a first region with a first impurity concentration and a second region with a second impurity concentration different from the first are created within the common semiconductor layer. This segmentation allows different portions of the same layer to serve different functions: one region provides good electrical contact while another region ensures proper cut-off characteristics for the select transistors.
Solution Approach 2:
Different impurity concentrations are introduced at different locations within the common semiconductor layer. The first region has a specific impurity concentration optimized for electrical connection, while the second region has a different impurity concentration optimized for transistor cut-off characteristics. This local quality variation resolves the contradiction by allowing each region to be optimized for its specific function rather than requiring uniform properties throughout the entire layer.
2Productivity
If one common drain electrode is connected to memory strings, then the degree of memory cell integration is improved, but unnecessary currents are passed through unselected memory strings
Solution Approach 1:
The common semiconductor layer is segmented into regions with different impurity concentrations to create functional zones. The segmentation creates a pathway that allows current to flow through selected memory strings while blocking current through unselected strings via the region with appropriate impurity concentration for cut-off characteristics.
Solution Approach 2:
The impurity concentration parameter is changed at different locations within the common semiconductor layer. By varying this parameter, the electrical properties of different regions are modified: one region maintains low resistance for current flow while another region creates high resistance to prevent current leakage through unselected memory strings.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure in which a first insulating layer, a first semiconductor layer, . . . an n-th insulating layer, an n-th semiconductor layer, and an (n+1)-th insulating layer (n is a natural number equal to or more than 2) are stacked in order thereof in a first direction perpendicular to a surface of a semiconductor substrate and which extends in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory strings which use the first to n-th semiconductor layers as channels respectively, a common semiconductor layer which combines the first to n-th semiconductor layers at first ends of the first to n-th memory strings in the second direction.