FinFET abrupt junctions via recess etching and spacer-defined doping
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Solution Overview
Problem
Conventional junction engineering in CMOS technology faces challenges in forming sharp junctions between the source/drain region and the device channel, particularly with semiconductor fins, as doped epitaxy material is too far away from the channel, leading to poor diffusion and manufacturability issues.
Innovation Solution
A method of forming FinFET devices with abrupt junctions by creating semiconductor fin portions on pedestal insulator portions, using dielectric spacers to protect areas during etching, and diffusing dopants from doped semiconductor material to form source and drain regions with sharp junctions, ensuring consistency and manufacturability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If doped epitaxy material is used to form source/drain regions, then the source/drain regions can be formed, but the junctions between source/drain region and channel are not sharp because the doped epitaxy material is too far away from the channel
Solution Approach 1:
The patent performs preliminary actions by forming dielectric spacers and performing recess etching before depositing the doped semiconductor material. This preliminary structuring brings the doped material closer to the channel region, enabling sharp junctions while maintaining manufacturability through a structured sequence of operations.
Solution Approach 2:
The patent segments the formation process into distinct stages: forming dielectric spacers, performing recess etching to create fin portions, then depositing doped material. This segmentation allows precise control over the distance between doped material and channel, achieving sharp junctions while keeping each step manufacturable.
2Productivity
If conventional scaling is continued to improve MOSFET performance, then device density increases, but scaling limits are reached making further performance improvement difficult
Solution Approach 1:
The patent transitions from planar MOSFETs to FinFETs, utilizing the vertical dimension by creating fins that protrude from the substrate. This dimensional change increases the effective channel area and gate control without further scaling the planar dimensions, thereby improving performance while avoiding scaling limits.
Solution Approach 2:
The patent changes the structural parameters by forming vertical fins with specific heights and widths, and by controlling the doping concentration and diffusion depth. These parameter changes enable continued performance improvement through enhanced carrier mobility and gate control rather than further planar scaling.
3Reliability
If FinFET structure is adopted to increase on-current per unit area, then device performance improves, but forming sharp junctions becomes more difficult
Solution Approach 1:
The patent introduces dielectric spacers as intermediary structures that define the precise location where doped material will be deposited. These spacers act as mediators between the gate structure and the source/drain regions, ensuring sharp junctions are formed at the correct positions while maintaining the FinFET structure's high on-current capability.
Solution Approach 2:
The patent performs preliminary formation of dielectric spacers and recess etching before depositing doped material. This preliminary structuring creates well-defined regions that guide subsequent doping, achieving sharp junctions in the FinFET structure without compromising the on-current performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the formation of FinFET devices with sharp junctions, improving device performance by ensuring precise dopant diffusion and consistent manufacturing, overcoming the limitations of traditional junction engineering.
Implementation Method 1
an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions
Data Source
AI summary
A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers.