FinFET Blocking Layer Prevents Ion Implantation Damage

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Solution Overview

Problem

The challenge in semiconductor manufacturing lies in forming reliable three-dimensional fin-like field effect transistors (FinFETs) as feature sizes decrease, making fabrication processes increasingly difficult due to issues like short channel effects and leakage current.

Innovation Solution

A semiconductor device structure is formed by creating a doped anti-punch-through region on a substrate, followed by a blocking layer, multiple semiconductor layers, and fin structures, with a gate stack encircling the fin channel structures to control them from multiple sides, and source/drain structures are formed adjacent to the fin channel structures to enhance performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If feature sizes continue to decrease to increase production efficiency and lower costs, then productivity improves, but manufacturing precision deteriorates due to increasingly difficult fabrication processes

Engineering Contradiction:
Improveproduction efficiencyVSAvoidfabrication process precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The fabrication process is divided into multiple sequential steps: forming the blocking layer first, then creating the fin structure, and finally performing ion implantation. This segmentation allows each step to be optimized independently, enabling precise control at smaller feature sizes while maintaining overall productivity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The blocking layer is formed in advance before the fin structure is created. This preliminary action protects the substrate and controls dopant diffusion paths before the critical fin formation occurs, enabling higher precision fabrication at scaled dimensions

Inventive Principle:
Principle #10Preliminary action

2Reliability

If ion implantation is performed to dope the substrate, then electrical properties improve, but fin structures may be damaged during the process

Engineering Contradiction:
Improvedevice reliabilityVSAvoidfin structure integrity
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The blocking layer is formed before ion implantation to define precise dopant diffusion boundaries. This preliminary structure guides the ion implantation process, ensuring dopants are deposited only in desired regions without damaging the fin structures

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The blocking layer acts as an intermediary between the ion implantation process and the fin structure. It mediates the dopant delivery, allowing electrical doping while protecting the fin structure from direct ion bombardment damage

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If a gate is provided over the fin to control the channel, then device performance improves, but leakage current occurs due to short channel effects

Engineering Contradiction:
Improvedevice performanceVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The planar gate structure is transformed into a three-dimensional FinFET structure where the gate wraps around the fin channel from multiple sides. This dimensional change increases the effective gate control over the channel, suppressing short channel effects and reducing leakage current while maintaining high device performance

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves device quality and reliability by preventing damage to fin structures during ion implantation, reducing leakage current, and enhancing carrier mobility, thereby achieving better performance and reliability in FinFETs.

Implementation Method 1

a blocking layer between the fin channel structure and the doped region

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Implementation Method 2

forming an anti-punch-through region over a semiconductor substrate

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS9761723B2Structure and formation method of finFET device
Publication Date: 2017.09.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9761723B2 patent drawing
  • US9761723B2 patent drawing
  • US9761723B2 patent drawing

AI summary

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a fin channel structure over the semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin channel structure. The semiconductor device structure further includes a source/drain structure adjacent to the fin channel structure and a doped region between the semiconductor substrate and the fin channel structure. In addition, the semiconductor device structure includes a blocking layer between the fin channel structure and the doped region.