FinFET Source/Drain Cavity Depth Uniformity via Low-k Spacers
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Solution Overview
Problem
In the fabrication of integrated circuit (IC) devices, particularly fin-type field-effect-transistor (FINFET) ICs, there is a challenge in creating uniform source/drain cavities due to depth differences caused by prior surface modifications, leading to irregular material levels and surfaces that complicate contact formation.
Innovation Solution
The method involves forming a hard mask on a silicon substrate, creating low-k dielectric spacers between STI regions, filling the openings with oxide, and epitaxially growing source/drain materials to ensure uniform cavity depths and surfaces, thereby achieving coplanar material levels across the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a recess is formed around the STI region to prevent side oxide loss during fin reveal, then oxide loss is prevented, but the cavity depth becomes non-uniform and material filling becomes irregular
Solution Approach 1:
The patent applies preliminary action by forming the recess around the STI region before the fin reveal process. This pre-formed recess structure prevents side oxide loss during the subsequent fin reveal step, while the recess depth is carefully controlled to not exceed the fin height, thereby maintaining cavity depth uniformity and enabling regular material filling in the source/drain regions.
2Reliability
If the recess depth is increased to better protect against oxide loss, then oxide loss prevention is improved, but the cavity depth non-uniformity increases and material levels become more irregular
Solution Approach 1:
The patent applies parameter changes by precisely controlling the recess depth parameter. The recess depth is set to be less than or equal to the fin height, which is an optimized parameter that balances two requirements: providing sufficient protection against side oxide loss during fin reveal, while maintaining uniform cavity depths for regular material filling. This parameter optimization resolves the contradiction between oxide loss prevention and material level uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in uniform source/drain cavities with consistent material levels, facilitating better contact formation and improving the overall integrity of the IC device by eliminating depth discrepancies and ensuring uniform material growth.
Implementation Method 1
forming low-k dielectric spacers on a lower portion of sidewalls of the opening, the spacers being formed between the sidewalls and the STI region
Implementation Method 2
epitaxially (epi) grown in the cavities 107a to 107d to respective levels 111a to 111d
Data Source
AI summary
Methods for creating uniform source/drain cavities filled with uniform levels of materials in an IC device and resulting devices are disclosed. Embodiments include forming a hard mask on an upper surface of a Si substrate, the hard mask having an opening over a STI region formed in the Si substrate and extending over adjacent portions of the Si substrate; forming low-k dielectric spacers on a lower portion of sidewalls of the opening, the spacers being formed between the sidewalls and the STI region; filling the opening with an oxide; removing the hard mask; removing an upper portion of the oxide and a portion of the low-k dielectric spacers; revealing a Si fin in the Si substrate; forming equally spaced gate electrodes, each having sidewall spacers, over the Si fin and the oxide; and forming source/drain regions in the Si fin between each pair of adjacent gate electrodes.