FinFET Channel Backside Passivation Layer for Oxidation Control
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Solution Overview
Problem
As transistors shrink in size, maintaining predictable performance becomes challenging due to minor processing variations affecting FinFET switching characteristics, particularly when III-V semiconductor channels are not adequately passivated, leading to incomplete control by the gate.
Innovation Solution
The implementation of a channel backside passivation layer (CBPL) using materials like indium phosphide or gallium antimonide to prevent oxidation and ensure complete passivation of the channel surface, thereby maintaining control over current flow and reducing the impact of processing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a III-V semiconductor channel is formed over an aluminum-based buffer layer without additional passivation, then device complexity is reduced, but the channel surface oxidizes and becomes conductive, degrading gate control and device performance
Solution Approach 1:
A channel backside passivation layer is formed over the aluminum-based buffer layer before forming the III-V semiconductor channel layer. This preliminary passivation prevents oxidation of the buffer layer during subsequent processing steps, ensuring the channel surface remains non-conductive and gate control is maintained throughout device fabrication and operation.
2Ease of manufacture
If the buffer layer extends above adjacent STI structures, then manufacturing is simplified, but the exposed buffer layer oxidizes and creates a conductive surface that degrades device performance
Solution Approach 1:
The channel backside passivation layer is deposited over the buffer layer before any etching or processing that would expose the buffer surface. This ensures that even if the buffer layer extends above STI structures, the exposed surfaces are already protected from oxidation, eliminating the harmful effect while maintaining manufacturing simplicity.
3Productivity
If minor processing variations occur during FinFET fabrication, then productivity is maintained, but switching characteristics degrade when the channel is not adequately passivated
Solution Approach 1:
The channel backside passivation layer serves as a protective cushion against processing variations. By preventing oxidation of the buffer layer beforehand, it creates a stable foundation that buffers against the effects of minor processing deviations, ensuring consistent switching characteristics despite variations in fabrication conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CBPL effectively prevents oxidation of aluminum-based buffer layers, ensuring stable and predictable performance of FinFETs by maintaining the gate's control over the channel region, even in the presence of minor processing variations.
Implementation Method 1
The implementation of a channel backside passivation layer (CBPL) using materials like indium phosphide or gallium antimonide to prevent oxidation
Data Source
AI summary
A FinFET with backside passivation layer comprises a template layer disposed on a substrate, a buffer layer disposed over the template layer, a channel backside passivation layer disposed over the buffer layer and a channel layer disposed over the channel backside passivation layer. A gate insulator layer is disposed over and in contact with the channel layer and the channel backside passivation layer. The buffer layer optionally comprises aluminum and the channel layer may optionally comprise a III-V semiconductor compound. STIs may be disposed on opposite sides of the channel backside passivation layer, and the channel backside passivation layer may have a top surface disposed above the top surface of the STIs and a bottom surface disposed below the top surface of the STIs.