FinFET Channel Doping via Dummy Gate Masking
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Solution Overview
Problem
Conventional ion implantation methods for FinFETs result in dopant loss and random dopant fluctuations due to thin fin dimensions, leading to mobility degradation and uncontrollable threshold voltages, especially with free-standing amorphous fins that introduce crystal lattice defects during re-crystallization.
Innovation Solution
The process involves forming a dummy gate over a central fin portion, replacing exterior fin portions with epitaxially-grown silicon-containing material, using a gate oxide for precise ion implantation, and employing polysilicon spacers to minimize dopant loss and annealing damage, allowing for controlled threshold voltage management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional ion implantation is performed before fin formation, then multiple threshold voltages are feasible, but dopant loss occurs due to thin fin dimensions and large surface to volume ratios
Solution Approach 1:
The fin structure is formed first, then ion implantation is performed after fin formation rather than before. This preliminary structuring allows the subsequent doping process to be more precisely controlled, reducing dopant loss that would otherwise occur due to the thin fin dimensions and large surface to volume ratio.
Solution Approach 2:
An annealing process is introduced as an intermediary step after ion implantation to re-crystallize the fins. This mediator reduces crystal lattice defects and minimizes dopant loss, thereby preserving the dopant concentration while maintaining the ability to achieve multiple threshold voltages.
2Manufacturing precision
If ion implantation is performed after fin formation, then dopant control is improved, but annealing introduces crystal lattice defects causing mobility degradation
Solution Approach 1:
The annealing process parameters are optimized to achieve re-crystallization with minimal damage. By carefully controlling temperature, time, and atmosphere parameters, the process achieves sufficient crystal structure recovery while minimizing the introduction of new lattice defects that would degrade carrier mobility.
Solution Approach 2:
The process combines ion implantation with selective annealing to create a composite effect: the implantation provides precise dopant placement while the annealing restores crystal structure. This composite approach achieves both precise dopant control and acceptable mobility by leveraging the complementary strengths of both processes.
3Ease of manufacture
If free standing fins are used, then fin formation is simplified, but re-crystallization introduces high levels of crystal lattice defects
Solution Approach 1:
The annealing process serves as a mediator between the simple free-standing fin formation and the final crystal structure. It provides the necessary re-crystallization to reduce lattice defects while maintaining the manufacturing simplicity of free-standing fins, acting as a bridge that preserves both ease of manufacture and crystal quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise dopant control and reduced mobility degradation by encapsulating the fin with a gate oxide and polysilicon spacers, maintaining stress retention and improving threshold voltage controllability.
Implementation Method 1
encapsulating the fin with a gate oxide and polysilicon spacers
Implementation Method 2
employing polysilicon spacers to minimize dopant loss and annealing damage
Implementation Method 3
implanting ions into the central portion of the fin through the gate oxide disposed over the central portion of the fin
Implementation Method 4
replacing exterior portions of the fin with an epitaxially-grown silicon-containing material
Implementation Method 5
performing an annealing process to re-crystallize the fin
Data Source
AI summary
An embodiment method of controlling threshold voltages in a fin field effect transistor (FinFET) includes forming a dummy gate over a central portion of a fin, the central portion of the fin disposed between exterior portions of the fin unprotected by the dummy gate, removing the exterior portions of the fin and replacing the exterior portions of the fin with an epitaxially-grown silicon-containing material, applying a spin-on resist over the dummy gate and the epitaxially-grown silicon-containing material and then removing the spin-on resist over the hard mask of the dummy gate, etching away the hard mask and a polysilicon of the dummy gate to expose a gate oxide of the dummy gate, the gate oxide disposed over the central portion of the fin, and implanting ions into the central portion of the fin through the gate oxide disposed over the central portion of the fin.