FinFET Dielectric Doping to Seal Air Gaps Near Contacts
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Solution Overview
Problem
As semiconductor devices, such as FinFETs, continue to shrink in feature size, they face challenges with increased capacitance between the gate stack and source/drain contacts, leading to reduced speed and reliability due to electrical shorts from conductive material entering air gaps.
Innovation Solution
The formation of air gaps surrounding source/drain epitaxial regions with a low dielectric constant, sealed by an expanded interlayer dielectric layer through dopant implantation, reduces capacitance and prevents conductive material from entering these gaps, thereby minimizing electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If air gaps are formed surrounding source/drain epitaxial regions to reduce capacitance, then speed and high-frequency performance are improved, but conductive material may enter the air gaps causing electrical shorts and reduced reliability
Solution Approach 1:
A seal structure is introduced as an intermediary element between the air gap and the conductive material. This seal structure prevents conductive material from entering the air gap while maintaining the low-capacitance benefit of the air gap, thus resolving the contradiction between speed improvement and reliability prevention
2Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but capacitance between gate stack and source/drain contacts increases leading to reduced speed
Solution Approach 1:
Air gaps with low dielectric constant are introduced locally between the gate stack and source/drain contacts. This local modification reduces the capacitance in the critical region without affecting the overall device scaling and integration density, thus resolving the contradiction between productivity and speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the speed and reliability of FinFET devices by reducing capacitance and preventing electrical shorts, allowing for faster operation and improved performance at higher frequencies.
Implementation Method 1
an expanded interlayer dielectric layer through dopant implantation
Data Source
AI summary
A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.