FinFET Diffusion Break Formation Without EUV Lithography
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Solution Overview
Problem
The existing methods for forming diffusion break structures in fin field effect transistors face challenges such as non-full cut-off defects due to photoresist bridging, which limits the integration level and increases costs with the need for expensive extreme ultraviolet lithography.
Innovation Solution
A method involving a lithography process to form a single diffusion break structure, followed by epitaxial growth and etching to create fin structures with an isolation layer, allowing for reduced bridge defects and improved process windows, thereby avoiding the need for expensive EUVL and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography is used to form diffusion break structures, then manufacturing cost is reduced, but photoresist bridging occurs causing non-full cut-off defects
Solution Approach 1:
The patent divides the formation process into two separate lithography steps: first forming the fin structure, then forming the diffusion break structure. This segmentation allows each structure to be optimized independently, preventing photoresist bridging while maintaining manufacturing feasibility with conventional lithography tools
Solution Approach 2:
The fin structure is formed first as a preliminary step before forming the diffusion break structure. This preliminary action establishes a foundation that enables subsequent precise formation of the diffusion break structure without interference, eliminating the bridging defect while using cost-effective conventional lithography
2Manufacturing precision
If extreme ultraviolet lithography (EUVL) is used to avoid photoresist bridging, then manufacturing precision is improved, but manufacturing cost increases significantly
Solution Approach 1:
By segmenting the lithography process into two separate conventional lithography steps, the patent achieves the precision of EUVL without incurring its high cost. Each step uses standard lithography tools, making the process economically viable while still preventing photoresist bridging defects
Solution Approach 2:
The preliminary formation of the fin structure using conventional lithography creates a platform that enables subsequent precise formation of the diffusion break structure. This approach achieves high precision through process sequencing rather than relying on expensive EUVL technology
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the lithography process window, reduces bridge defects, and enhances product yield by allowing for flexible adjustment of device parameters, such as doping elements and gas flow rates, resulting in improved fin field effect transistor performance.
Implementation Method 1
performing an epitaxial growth process, and forming an epitaxial layer on a surface of the substrate, a bottom surface and side walls of the etched single diffusion break structure
Data Source
AI summary
A method is disclosed for forming a diffusion break structure in a fin field effect transistor, including: performing a lithography process on a substrate to form a lithography pattern of a single diffusion break structure; etching the substrate to form an etched single diffusion break structure; performing an epitaxial growth process, forming an epitaxial-layer-covered single diffusion break structure by depositing an epitaxial layer on the surface of the substrate and the bottom surface and sidewalls of the etched single diffusion break structure; etching the epitaxial layer and the substrate in the single diffusion break structure, to form a plurality of fins arranged at intervals; forming an isolation layer between the two adjacent fins, wherein the top surface of the fins is higher than the top surface of the isolation layer; and forming gates spaced apart from each other respectively at the top of the isolation layer.


