Semiconductor/Solid-State Device Manufacturing TRIZ Cases
- Ruthenium Etchant Composition for Low-RuO4 Patterning
A near-neutral periodic acid and ammonium etchant suppresses RuO4 gas while keeping ruthenium etch rate and room-temperature stability.
- Quantized Metal Contacts for Low-Resistance Semiconductor Interfaces
Graded quantized metal contacts smooth band discontinuities and reduce Fermi level pinning to lower semiconductor contact resistance.
- FinFET Diffusion Break Formation Without EUV Lithography
A segmented lithography and epitaxy flow forms FinFET diffusion breaks with fewer bridge defects, wider process windows, and better yield.
- Silicon Carbide Substrate Thinning by Ion-Implanted Separation
Ion implantation and annealing thin a silicon carbide substrate without grinding, reducing tool wear, surface damage, and substrate waste.
- EFEM Wafer Cleaning and Drying for Corrosion-Free FOUP Return
Integrated wafer cleaning and N2 drying remove residual halogen and ammonia before FOUP return, cutting corrosion risk and treatment time.
- Split-Gate Flash Memory Cell Layout With Self-Aligned Gate Formation
Self-aligned polysilicon etching forms split-gate flash and logic regions with precise gate dimensions and fewer deposition steps.
- Engineered Glass Carrier Substrates With Controlled Edge Stress
Controlled cooling creates edge compression and center tension in glass carrier substrates, improving flatness and handling compatibility.
- Thin-Film Transistor Cu Buffer Layers for Low-Resistance Adhesion
Cu alloy buffer layers and metal oxide isolating layers improve TFT adhesion, protect the semiconductor, and reduce image signal delay.
- Organic Film Planarizing Agent for Fine Pattern Filling and Etch Resistance
An aromatic planarizing agent lowers high-temperature viscosity to fill fine holes and trenches without voids while maintaining etching resistance.
- SiOCN Film Formation for Low-Temperature Etch Stop Layers
Thermal cyclic ALD forms SiOCN films with lower wet etch rates at 300-600 C, enabling spacers and etch stop layers in electronic devices.
- Mixed 1D and Crossbar Fin Transistors for Stable GAA Scaling
Spacer-defined odd and crossbar fin formation improves GAA transistor density while reducing shorts and preserving channel stability.
- Recessed Active Region Memory Layout With Protruding Drain Contacts
A recessed active region and protruding drain layout cuts memory cell pitch while preserving channel length and easing dense MONOS fabrication.
- LDMOS RESURF Layer Layout for Low On-Resistance and High Breakdown
A localized implanted RESURF layer and tuned spacing help LDMOS transistors balance low on-resistance with higher breakdown voltage.
- UV-Ozone Photoresist Removal Nozzle for Uniform Strip Rate
UV irradiation of an ozone-containing slit nozzle improves photoresist strip uniformity across the substrate while avoiding sulfuric-acid waste.
- Top Plate Rinsing in Wafer Processing to Cut Atmosphere Gas Use
A close top plate and shared rinsing liquid shrink wafer-process space, reducing atmosphere gas use while keeping processing reliable.
- Wafer Backside Cleaning for Flatness and Exposure Accuracy
Region-specific backside brush cleaning removes wafer contaminants only where needed, improving flatness and lithography exposure accuracy.
- Silicon Nitride Spacer Formation for Leakage-Safe Metal Drains
A sacrificial silicon nitride layer preserves drain spacers during etching to reduce current leakage and DVC/BVC defects.
- Multiple Sidewall Spacers for Gate Dielectric Protection
Protective and sacrificial sidewall spacers create air gaps that limit gate dielectric etch damage, reducing leakage and stabilizing threshold voltage.
- Protruded Field Plate in Nitride Semiconductors for Higher Gain
A protruded field plate over stacked nitride layers cuts gate-drain capacitance and raises gain by adjusting two-dimensional electron gas density.
- Source-Coupled Cap Structure for HEMT Saturation Current Control
A source-coupled cap partially depletes the HEMT channel to curb saturation current and improve high-voltage reliability.
- EUV Mask Multilayer Structure for Reduced Wafer Neighboring Effects
A dual reflective multilayer and absorption stack cuts wafer neighboring effects, limiting mask contamination and defectivity in EUV lithography.
- Nitride Semiconductor Source Region Deposition After Dehydrogenation
Dehydrogenation annealing followed by deposited-film source formation avoids ion implantation defects and impurity mixing in nitride semiconductors.
- Resist Composition Inspection via Coating Removal Defect Transfer
By stripping an unexposed coating film and counting substrate defects, this case detects ultra-small foreign substances in resist compositions.
- Alloy Thin Film ALD Without Oxygen or Nitriding Steps
Forms alloy thin films by ALD without oxygen or nitrogen gases, improving step coverage and lowering oxygen ratio while simplifying MOS electrode deposition.
- Movable Preheating Ring Alignment for Uniform Epitaxial Wafers
A movable preheating ring follows susceptor height changes to reduce gas-flow turbulence and film thickness variation in epitaxial wafer growth.
- Air-Layer Heating Unit for Uniform Substrate Bake Temperature
Internal air layers above and beside the heater cut bake-chamber heat loss, improving substrate temperature uniformity and heating response.
- GaN HEMT Heterostructure on Resistive SiC for Low Conduction Loss
A resistive SiC epitaxial layer cuts substrate conductivity and defects, enabling lower-loss GaN HEMTs with better RF performance.