Trench MOSFET Structure Using Fixed Charge to Cut Rsp and Capacitance
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Solution Overview
Problem
Conventional trench MOSFETs face challenges in minimizing specific on-resistance (Rsp) and associated capacitances due to increased cell density, which leads to higher gate drain capacitance (Cgd) and gate source capacitance (Cgs), resulting in increased power loss.
Innovation Solution
The use of power MOSFET structures with gate-to-source, gate-to-drain, or both gate-to-source and gate-to-drain offsets, incorporating dielectric layers with intentionally introduced permanent charges to create induced source or drain extensions, allowing for shorter channel lengths and reduced capacitances by forming an inversion layer at the silicon-dielectric interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If cell density is increased to reduce device area, then device integration is improved, but gate drain and gate source capacitances increase leading to higher power loss
Solution Approach 1:
The patent introduces a third dimension by forming an inversion layer at the silicon-dielectric interface through permanent charges in the dielectric layer. This vertical field effect creates induced source and drain extensions that extend the effective channel length without increasing lateral dimensions, thereby reducing capacitances while maintaining high cell density
Solution Approach 2:
The patent changes the electrical parameters of the dielectric layer by introducing permanent charges, which fundamentally alters the electric field distribution. This creates depletion regions and inversion layers that modify the effective channel characteristics, reducing gate-to-drain and gate-to-source capacitances without changing the physical device area
2Loss of energy
If channel length is reduced to lower on-resistance, then conduction loss is reduced, but gate drain and gate source capacitances increase
Solution Approach 1:
The patent uses the vertical dimension by creating an inversion layer at the silicon-dielectric interface. This vertical field effect induces source and drain extensions that effectively lengthen the channel in the vertical direction, allowing shorter lateral channel lengths for lower on-resistance while maintaining adequate electrical length to control capacitances
Solution Approach 2:
The permanent charges in the dielectric layer act as an intermediary that creates depletion regions and inversion layers. These intermediary structures effectively extend the channel length without physically lengthening the lateral dimension, thereby reducing on-resistance while controlling capacitance through the induced charge distributions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces specific on-resistance (Rsp), gate-to-drain capacitance (Cgd), and gate-to-source capacitance (Cgs), thereby minimizing power loss in power MOS transistors.
Implementation Method 1
at least some portions of the insulating material contain fixed electrostatic charge in a density high enough to deplete a second portion of the semiconductor material when no voltage is applied
Implementation Method 2
A gate electrode within the trench is capacitively coupled through the insulating material to a first portion of the semiconductor material
Data Source
AI summary
A vertical device structure includes a volume of semiconductor material, laterally adjoining a trench having insulating material on sidewalls thereof. A gate electrode within the trench is capacitively coupled through the insulating material to a first portion of the semiconducting material. Some portions of the insulating material contain fixed electrostatic charge in a density high enough to invert a second portion of the semiconductor material when no voltage is applied. The inverted portions can be used as induced source or drain extensions, to assure that parasitic are reduced without increasing on-resistance.