Hardened Memory Cell Feedback Decoupling for Transient Error Protection
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Solution Overview
Problem
Conventional memory cells are not optimal in terms of protection against transient disturbances, speed, and flexibility, particularly due to increased surface cost and write time, and existing solutions either require additional manufacturing steps or compromise on data integrity during ionizing particle events.
Innovation Solution
A memory cell design incorporating decoupling transistors in feedback loops that are permanently off, creating high impedance states to delay transient errors and utilize leakage currents to maintain data integrity, while minimizing surface area and avoiding additional manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If resistors are connected in the feedback loop to protect against transient disturbances, then reliability is improved, but speed deteriorates
Solution Approach 1:
The patent removes resistors from the feedback loop entirely, extracting the harmful element that caused the speed limitation. Instead of using resistors to delay transient propagation, the invention uses a different mechanism (transistor switching) that achieves protection without the speed penalty imposed by resistive elements.
Solution Approach 2:
The patent changes the operational state of transistors (from always-on to switchable off-state) to dynamically control feedback loop behavior. By switching transistors off during store phases, the feedback loop is effectively opened, providing protection without the continuous speed limitation that resistors would impose.
2Reliability
If resistors are added to the feedback loop for hardening, then protection against ionizing particles is improved, but device complexity increases
Solution Approach 1:
The patent makes existing transistors serve multiple functions: they act as both the inverter switching elements and the feedback control elements. By switching transistors off during store phases, the same transistor provides both logic function and protection function, eliminating the need for separate resistor components and their associated manufacturing steps.
Solution Approach 2:
The patent merges the protection function with the existing inverter transistors. The feedback loop uses the same transistors that constitute the inverter logic, combining what would traditionally be separate components (inverter elements and protection elements) into a unified structure that reduces manufacturing complexity.
3Reliability
If isolation resistors are used in series between transistors, then protection is improved, but write time increases
Solution Approach 1:
The patent introduces dynamic control of the feedback loop through clocked switching of transistors. During write phases, transistors are kept on to allow rapid data writing; during store phases, transistors are switched off to provide protection. This dynamic behavior eliminates the static time penalty that series resistors would impose on write operations.
Solution Approach 2:
The patent uses periodic clock signals to control the switching state of transistors in the feedback loop. The clock rhythmically switches transistors on during write phases and off during store phases, creating periodic windows for fast writing followed by protection periods, thereby avoiding continuous write time extension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The memory cell effectively protects against transient disturbances by maintaining data integrity through leakage currents, minimizing surface area, and ensuring high-speed operations without increasing write time or manufacturing complexity.
Implementation Method 1
incorporating decoupling transistors in feedback loops that are permanently off, creating high impedance states to delay transient errors
Implementation Method 2
utilize leakage currents to maintain data integrity... the leakage currents flowing between the source and drain of these transistors are sufficient to compensate the losses due to the leakage currents of the cell
Data Source
AI summary
The memory cell comprises first and second inverter circuits, connected in a loop. First and second decoupling transistors, normally turned off outside the write phases, are respectively connected between an output of the second inverter circuit and first and second inputs of the first inverter circuit. The memory cell is thereby protected against transient disturbances due to ionizing particles. The gates of the decoupling transistors are preferably respectively connected to a supply voltage for the P-type decoupling transistors and grounded for the N-type decoupling transistors.