Strained Source/Drain CMOS Integration with Oxide Hard Mask
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Solution Overview
Problem
Conventional integrated circuit manufacturing processes face challenges in reducing device size and improving switching speed due to limitations in materials and complex manufacturing processes, particularly in the integration of PMOS and NMOS devices within CMOS technologies.
Innovation Solution
The integration of PMOS and NMOS devices using strained silicon structures, where silicon germanium and silicon carbide epitaxial films are selectively grown in recessed regions of the silicon substrate, with a reduced number of process steps and minimal degradation of polysilicon gate spacers and shallow trench isolation, allowing for compressive and tensile strain modes in channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional manufacturing processes are used to reduce device size, then device geometry becomes smaller, but process limitations prevent further scaling and manufacturing complexity increases
Solution Approach 1:
The patent applies parameter changes by introducing strained silicon structures with controlled strain levels (compressive or tensile strain up to 1%) to modify the physical properties of the semiconductor channel. This allows continued scaling to smaller geometries (90nm and below) by changing the strain state rather than simply reducing dimensions, thereby overcoming conventional process limitations without proportionally increasing manufacturing complexity
Solution Approach 2:
The patent employs composite materials by integrating silicon germanium (SiGe) and silicon carbide (SiC) epitaxial films with silicon substrate to create strained silicon structures. These composite material systems enable enhanced carrier mobility and device performance at scaled dimensions, allowing further miniaturization while maintaining manufacturability through established epitaxial growth processes
2Productivity
If device size is reduced to increase circuit density, then more devices fit on each wafer, but switching speed and signal clarity deteriorate
Solution Approach 1:
The patent changes the strain parameter in the silicon channel to enhance carrier mobility. By introducing compressive strain for PMOS devices and tensile strain for NMOS devices, the effective mass of carriers is reduced and mobility is enhanced, thereby maintaining fast switching speeds even as device dimensions are reduced to increase circuit density
Solution Approach 2:
The patent applies local quality by selectively introducing strain only in the channel region where it is most needed for performance enhancement. The strained silicon structures are locally engineered in the active channel area while maintaining standard structures in other regions, allowing speed enhancement without affecting overall device scaling and density
3Reliability
If advanced strained silicon structures are used to improve performance, then device yields and mobility increase, but manufacturing process complexity increases
Solution Approach 1:
The patent applies segmentation by separating the strain engineering into distinct process modules: first forming the basic CMOS structure, then selectively adding strained silicon layers in specific regions (PMOS regions with compressive strain, NMOS regions with tensile strain). This modular approach improves device yields through better performance control while managing complexity by breaking down the integration scheme into manageable, sequential process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device yields, maintains compatibility with conventional technology, and supports design rules of 90 nanometers and less, while increasing hole mobility and simplifying the manufacturing process, thereby improving the integration and performance of CMOS devices.
Implementation Method 1
silicon germanium and silicon carbide epitaxial films are selectively grown in recessed regions of the silicon substrate
Implementation Method 2
allowing for compressive and tensile strain modes in channel regions
Data Source
AI summary
A method for forming a semiconductor integrated circuit device, e.g., CMOS, includes providing a semiconductor substrate having a first well region and a second well region. The method further includes forming a dielectric layer overlying the semiconductor substrate, the first well region and the second well region, and forming a polysilicon gate layer (e.g., doped polysilicon) overlying the dielectric layer. The polysilicon gate layer is overlying a first channel region in the first well region and a second channel region in the second well region. The method includes forming a hard mask (e.g., silicon dioxide) overlying the polysilicon gate layer and patterning the polysilicon gate layer and the hard mask layer to form a first gate structure including first edges in the first well region and a second gate structure including second edges in the second well region. Next, the method separately forms strained regions in the first and second well regions.