Split-Gate Flash Memory Cell Layout With Self-Aligned Gate Formation
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Solution Overview
Problem
The formation of non-volatile flash memory cells with select, floating, control, and erase gates on a shared substrate is challenging due to difficulties in controlling relative dimensions, leading to complex manufacturing processes.
Innovation Solution
A method for forming non-volatile memory cells involving the sequential deposition and etching of silicon dioxide and polysilicon layers, with the use of composite insulating layers and spacers to define the gates, allowing for self-aligned formation of select and erase gates without additional poly deposition steps, thereby simplifying the process and reducing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional methods are used to form memory cells with four gates and logic circuits on the same substrate, then both memory and logic devices can be integrated, but control of relative dimensions becomes difficult and manufacturing complexity increases
Solution Approach 1:
The substrate is divided into distinct memory cell regions and logic circuit regions, with selective area etching and deposition processes applied to each region. This segmentation allows different structures (memory cells with four gates vs. logic circuits) to be formed on the same substrate without interfering with each other, resolving the contradiction between integration capability and manufacturing complexity
Solution Approach 2:
The method performs preliminary formation of the floating gate and control gate structures before forming the select and erase gates. By establishing the floating gate first as a reference structure, subsequent gates can be self-aligned to it, ensuring precise relative dimensions are achieved without requiring complex dimensional control during manufacturing
2Manufacturing precision
If additional poly deposition steps are used to form select and erase gates, then precise gate dimensions can be achieved, but manufacturing process complexity increases
Solution Approach 1:
The floating gate and control gate structures serve as self-aligned masks and references for forming the select and erase gates. The etching processes use these pre-formed structures to automatically define the positions and dimensions of the subsequent gates, eliminating the need for additional poly deposition steps while maintaining precise dimensional control through self-alignment mechanisms
Solution Approach 2:
The floating gate is formed in advance as a preliminary structure that defines the spatial relationships for all subsequent gates. This preliminary action establishes a reference framework that guides the formation of control, select, and erase gates, ensuring precise relative dimensions are achieved without requiring complex dimensional control during manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables simpler and more robust formation of memory cells with precise gate dimensions, reducing manufacturing complexity and eliminating the need for dummy poly layers or additional poly deposition, while allowing for the formation of both memory and logic devices on the same substrate.
Implementation Method 1
sequential deposition and etching of silicon dioxide and polysilicon layers
Implementation Method 2
sequential deposition and etching of silicon dioxide and polysilicon layers
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E
AI summary
A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.