Semiconductor Isolation Pillars via Dummy Fin Removal
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As device integration densities increase, such as at 10 nm and beyond, FINFET semiconductor devices face challenges with inadvertent shorting due to reduced spacing between adjacent devices, and existing isolation methods like raised shallow trench isolation are difficult to precisely control, potentially leading to increased 'on' resistance and device damage.
Innovation Solution
A self-aligned 'dummy fin' approach is used to prevent epitaxial lateral growth in N/P transistor boundary regions by selectively removing intermediate semiconductor fins to create isolation pillars, which are formed from a different dielectric material than the initial dielectric material between the fins, allowing for precise control and preventing shorts while maintaining chip area scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If raised shallow trench isolation is used to prevent shorting between adjacent devices, then isolation between devices is improved, but manufacturing precision deteriorates due to difficulty in precise control
Solution Approach 1:
The patent applies preliminary action by first forming a dummy fin structure before the isolation process. This dummy fin serves as a pre-positioned template that guides subsequent isolation material deposition, ensuring precise placement of isolation pillars before actual device fabrication begins. The dummy fin is later removed after serving its positioning purpose.
Solution Approach 2:
The dummy fin acts as an intermediary element that facilitates precise isolation pillar formation. It serves as a temporary structure that mediates between the lithography alignment and the final isolation structure placement, enabling accurate positioning without requiring direct alignment of isolation materials to the final device geometry.
2Productivity
If device integration density is increased to scale chip area, then productivity is improved, but device reliability deteriorates due to increased risk of inadvertent shorting
Solution Approach 1:
The patent applies segmentation by dividing the isolation structure into two distinct parts: a first dielectric material filling the shallow trench isolation region and a second dielectric material forming the isolation pillar. This segmentation allows each material to be optimized independently - the first for trench filling and the second for precise pillar formation and short prevention.
Solution Approach 2:
The dummy fin serves as an intermediary that enables high-density integration while maintaining reliability. It provides a physical reference that ensures isolation pillars are correctly positioned even as device spacing decreases, allowing higher integration density without increasing shorting risk.
3Reliability
If isolation pillars are positioned precisely to prevent shorting, then device reliability is improved, but device complexity increases due to additional process steps
Solution Approach 1:
The dummy fin structure is self-service in that it automatically provides the positioning reference needed for isolation pillar formation. The etch selectivity between the dummy fin and surrounding structures creates self-aligned features, eliminating the need for separate alignment steps and reducing overall process complexity despite adding the dummy fin formation step.
Data Source
AI summary
A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins.