GaN HEMT Heterostructure on Resistive SiC for Low Conduction Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
HEMT devices grown on silicon substrates suffer from high crystallographic defects leading to low electrical performance, while those grown on semi-insulating silicon carbide wafers are costly due to high costs associated with large-diameter wafers.
Innovation Solution
A HEMT device manufacturing process using a conductive silicon carbide wafer with a tilted off-axis surface, where an epitaxial highly resistive silicon carbide layer is grown to reduce crystallographic defects and lower substrate conductivity, followed by forming a heterostructure with a GaN channel and AlGaN barrier layer, allowing for low conduction losses and cost-effective production using large-diameter wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the heterostructure is grown on a resistive silicon substrate, then the conductive losses through the substrate are reduced, but the crystallographic defects increase leading to low electrical performance
Solution Approach 1:
The patent introduces an intermediate layer (buffer layer or epitaxial layer) between the silicon substrate and the GaN-based heterostructure. This intermediate layer acts as a mediator that reduces crystallographic defects and dislocation propagation from the silicon substrate to the active device layers, while still allowing the use of cost-effective silicon substrates with appropriate resistivity to minimize conductive losses.
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers with different material properties: a silicon substrate providing mechanical support and low cost, an intermediate buffer layer (such as SiC or AlN) that reduces defects, and the GaN-based heterostructure providing high electron mobility and low conductive losses. This composite approach combines the advantages of different materials while mitigating their individual disadvantages.
2Reliability
If the heterostructure is grown on a semi-insulating silicon carbide wafer, then the crystallographic defects are reduced improving electrical performance, but the manufacturing cost increases due to high wafer cost
Solution Approach 1:
The patent uses an intermediate buffer layer that enables the use of lower-cost substrates (such as conductive or semi-conductive silicon carbide or even silicon) while achieving defect densities comparable to those obtained on expensive semi-insulating silicon carbide wafers. The buffer layer mediates the interface between the substrate and the GaN heterostructure, reducing defect propagation.
Solution Approach 2:
The patent employs cheaper substrate materials (conductive or semi-conductive silicon carbide wafers, or even silicon substrates) instead of expensive semi-insulating silicon carbide wafers. The use of cost-effective substrates combined with advanced buffer layer techniques achieves acceptable defect levels at lower manufacturing costs.
3Productivity
If large-diameter silicon carbide wafers are used, then the productivity and manufacturing efficiency are improved, but the substrate cost increases
Solution Approach 1:
The patent employs conductive or semi-conductive silicon carbide wafers instead of expensive semi-insulating silicon carbide wafers. These cheaper substrates can be manufactured in large diameters (200mm or more) to improve productivity, while the use of buffer layers and optimized growth techniques ensures acceptable device performance despite the lower substrate cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process results in HEMT devices with improved electrical performance and reduced manufacturing costs by utilizing large-diameter silicon carbide wafers, achieving low conductive losses and enhanced RF performance.
Implementation Method 1
an epitaxial highly resistive silicon carbide layer is grown to reduce crystallographic defects and lower substrate conductivity
Implementation Method 2
a conductive channel is based on the formation of a two-dimensional electron gas (2DEG) having high mobility at a heterojunction, that is at the interface between semiconductor materials having different band gap
Data Source
AI summary
For the manufacturing of a HEMT device (50), from a wafer (2) of silicon carbide having a surface (2A), an epitaxial layer (4) of silicon carbide is formed on the surface (2A) of the wafer (2), a semiconductive heterostructure (5) is formed on the epitaxial layer, and the wafer of silicon carbide is removed.