Multiple Sidewall Spacers for Gate Dielectric Protection
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Solution Overview
Problem
The existing methods for fabricating MOS transistors damage the gate dielectric layer during the etching process, leading to increased leakage current, unstable threshold voltage, and reduced carrier mobility, which affects the performance of semiconductor devices.
Innovation Solution
The method involves forming first and second sidewall spacers made of different materials, with the second sidewall spacers being removed to create air gap spacers above the first sidewall spacers and between the conductive plugs, thereby reducing the damage to the gate dielectric layer and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching process is used to form sidewall spacers, then the gate dielectric layer is damaged, but this leads to increased leakage current and reduced device performance
Solution Approach 1:
A protective layer is introduced as an intermediary between the etching process and the gate dielectric layer. This protective layer absorbs the harmful effects of the etching process, preventing direct damage to the gate dielectric layer while still allowing the sidewall spacer formation to proceed. The protective layer is selectively removed after serving its protective function.
Solution Approach 2:
The protective layer is applied beforehand to cushion or buffer the gate dielectric layer against the subsequent etching process. This prior cushioning prevents the etching process from directly impacting the gate dielectric layer, thereby preventing damage before it can occur.
2Ease of manufacture
If gate dielectric layer is damaged during fabrication, then manufacturing process is simpler, but leakage current increases and threshold voltage becomes unstable
Solution Approach 1:
The protective layer serves as a mediator that allows the fabrication process to proceed without compromising device reliability. It enables the etching process to be performed while protecting the gate dielectric layer, thus maintaining threshold voltage stability without significantly complicating the manufacturing process.
3Productivity
If gate dielectric layer is damaged during fabrication, then manufacturing process is faster, but carrier mobility is reduced
Solution Approach 1:
The protective layer is applied in advance to cushion the gate dielectric layer during the fabrication process. This allows the manufacturing process to proceed at normal speed without causing damage to the gate dielectric layer, thereby maintaining carrier mobility while preserving productivity.
Data Source
AI summary
Semiconductor devices fabrication method is provided. The method for fabricating the semiconductor device includes: providing a semiconductor substrate; forming a gate structure on a surface of the semiconductor substrate; forming protective sidewall spacers on sidewall surfaces of the gate structure and to cover sidewall surfaces of the gate dielectric layer; forming sacrificial sidewall spacers on sidewall surfaces of the protective sidewall spacers and between the protective sidewall spacers and the gate structure; forming a first dielectric layer on the surface of the semiconductor substrate around the gate structure, the protective sidewall spacers and the sacrificial sidewall spacers; forming conductive plugs in the first dielectric layer at opposite sides of the gate structure, the protective sidewall spacers and the sacrificial sidewall spacers; and removing the sacrificial sidewall spacers to form air gap spacers between the protective sidewall spacers and the conductive plugs.