Magnetic Tunnel Junction Between Metal Layers Using Combined Mask Patterning
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Solution Overview
Problem
Conventional magnetic RAM (MRAM) manufacturing processes require multiple mask processes, increasing costs and reducing component density, which affects the cost and yield of memory systems.
Innovation Solution
A method for forming a magnetic tunnel junction (MTJ) between metal layers of a semiconductor device using no more than two masks, involving the formation of a first metal layer, a bottom electrode layer, a MTJ, a top electrode layer, and a second metal layer, with optional patterning of the bottom electrode layer using a second mask, and the use of an insulator layer to expose the top surface of the first metal layer for contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask processes are used for MTJ fabrication, then the MTJ structure can be formed with precise patterning, but the manufacturing cost increases and component density decreases
Solution Approach 1:
The patent combines the patterning of the top electrode layer and the MTJ into a single mask process. The method forms a combined mask structure that patterns both the top electrode and MTJ simultaneously, reducing the total number of mask processes from multiple separate steps to just one or two mask processes, thereby lowering manufacturing complexity and cost while maintaining patterning precision
Solution Approach 2:
The mask structure is designed to perform multiple functions: it patterns both the top electrode layer and the MTJ structure in the same process step. This multi-functional mask approach eliminates the need for separate dedicated masks for each layer, reducing the overall number of mask processes required for MTJ fabrication
2Manufacturing precision
If multiple mask processes are used for MTJ fabrication, then the MTJ structure can be formed with precise patterning, but the manufacturing cost increases
Solution Approach 1:
The patent combines the patterning of the top electrode layer and the MTJ into a single mask process. The method forms a combined mask structure that patterns both the top electrode and MTJ simultaneously, reducing the total number of mask processes from multiple separate steps to just one or two mask processes, thereby lowering manufacturing complexity and cost while maintaining patterning precision
Solution Approach 2:
The patent uses a sacrificial layer that is temporarily formed to enable the combined mask patterning process, then selectively removed after serving its purpose. This sacrificial layer allows the mask to be formed and patterned correctly, and is subsequently discarded, enabling the manufacturing process to proceed with fewer mask steps and lower cost
3Manufacturing precision
If multiple mask processes are used for MTJ fabrication, then the MTJ structure can be formed with precise patterning, but component density decreases
Solution Approach 1:
The patent combines the patterning of the top electrode layer and the MTJ into a single mask process. The method forms a combined mask structure that patterns both the top electrode and MTJ simultaneously, reducing the total number of mask processes from multiple separate steps to just one or two mask processes, thereby lowering manufacturing complexity and cost while maintaining patterning precision
Solution Approach 2:
The patent utilizes vertical layering and three-dimensional structuring to achieve precise patterning without requiring multiple lateral mask steps. By forming structures in the vertical dimension (stacking layers) and using selective etching from different directions, the method achieves precise MTJ patterning with fewer mask processes, enabling higher component density on the chip surface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall number of processing steps, decreases manufacturing costs, and allows for higher component density, enabling more cells to be packed onto a single chip, thus improving the cost-effectiveness and yield of memory production.
Implementation Method 1
Due to the tunneling magnetoresistance effect, the electrical resistance of the cell changes due to the orientation of the fields in the two plates
Data Source
AI summary
Embodiments herein provide a magnetic tunnel junction (MTJ) formed between metal layers of a semiconductor device. Specifically, provided is an approach for forming the semiconductor device using only one or two masks, the approach comprising: forming a first metal layer in a dielectric layer of the semiconductor device, forming a bottom electrode layer over the first metal layer, forming a MTJ over the bottom electrode layer, forming a top electrode layer over the MTJ, patterning the top electrode layer and the MTJ with a first mask, and forming a second metal layer over the top electrode layer. Optionally, the bottom electrode layer may be patterned using a second mask. Furthermore, in another embodiment, an insulator layer (e.g., manganese) is formed atop the dielectric layer, wherein a top surface of the first metal layer remains exposed following formation of the insulator layer such that the bottom electrode layer contacts the top surface of the first metal layer. By forming the MTJ between the metal layers using only one or two masks, the overall number of processing steps is reduced.