Embedded-Gate Graphene Structure for Lower-Voltage Channel Control
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Solution Overview
Problem
The manufacturing process of graphene devices is complex and affects the properties of graphene, particularly due to low coupling between the oxide layer and the global back gate, leading to increased operation voltage and complications in forming the oxide layer and gate electrode.
Innovation Solution
A graphene device with an embedded gate on a substrate, an upper oxide layer, and a graphene channel, along with a plurality of electrodes, is manufactured using a simplified process that includes forming an insulating layer and a metal pattern corresponding to the embedded gate, allowing for independent control of the graphene channel and reducing the complexity of the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a global back gate is formed on the oxide layer, then the device structure is complete, but the coupling between the oxide layer and the global back gate is relatively low, leading to increased operation voltage
Solution Approach 1:
The patent divides the gate structure into multiple embedded gates positioned at different locations beneath the graphene channel, rather than using a single global back gate. This segmentation allows each embedded gate to provide localized electrostatic control, improving coupling efficiency and reducing the operation voltage required to modulate the graphene channel.
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the embedded gates and the graphene channel. This insulating layer enables better electrostatic coupling while electrically isolating the gates, allowing for more effective control of the graphene channel with lower operating voltages compared to the direct coupling in global back gate configurations.
2Reliability
If the processes of forming the oxide layer and gate electrode on the oxide layer are used, then the device structure is formed, but the manufacturing process becomes complicated and the properties of graphene may change
Solution Approach 1:
The patent forms the embedded gates and insulating layer structures before transferring and positioning the graphene layer. This preliminary preparation of the substrate structure eliminates the need for subsequent high-temperature or chemically intensive processing steps that would be required to form gates on top of oxide layers, thereby simplifying the overall manufacturing process and preserving graphene properties.
Solution Approach 2:
Instead of forming the gate electrode on top of the oxide layer as in conventional approaches, the patent inverts the sequence by embedding gates beneath the oxide layer and graphene channel. This inversion allows the graphene to be transferred onto a pre-prepared structure, avoiding complex processing steps and maintaining graphene integrity.
3Stability of the object's composition
If the oxide layer thickness is increased to 300 nm, then the device structure is stable, but the coupling between the oxide layer and the global back gate becomes relatively low
Solution Approach 1:
By segmenting the gate structure into multiple embedded gates distributed beneath the oxide layer, the patent achieves effective electrostatic control without requiring thin oxide layers. Each embedded gate provides localized control, maintaining coupling efficiency even with thicker oxide layers that provide structural stability.
Solution Approach 2:
The patent transitions from a planar global back gate configuration to a three-dimensional embedded gate structure positioned at multiple depths and locations beneath the oxide layer. This dimensional change enables effective coupling through the oxide layer by placing control electrodes closer to the graphene channel in the vertical dimension, while the oxide layer maintains its stabilizing function.
Data Source
AI summary
Provided is a graphene device and a method of manufacturing the same. The graphene device may include an upper oxide layer on at least one embedded gate, and a graphene channel and a plurality of electrodes on the upper oxide layer. The at least one embedded gate may be formed on the substrate. The graphene channel may be formed on the plurality of electrodes, or the plurality of electrodes may be formed on the graphene channel.