MOS Gate Shielding Structure for Parasitic Coupling Reduction
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Solution Overview
Problem
As MOS device dimensions decrease, coupling between the regions of the MOS device increases due to the proximity of metallization layers and contacts, leading to significant parasitic capacitances that affect switching times and performance.
Innovation Solution
A shielding structure is disposed above the conductive gate of the MOS device to reduce capacitance between the terminals by providing an alternate path to ground, thereby reducing parasitic capacitances and mutual couplings between the source, drain, and gate regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metallization layers and contacts are placed in conventional positions to establish electrical connections, then electrical connectivity is achieved, but parasitic capacitances increase due to proximity coupling between terminals
Solution Approach 1:
A shielding structure is introduced as an intermediary element between the source and drain terminals. This shielding structure, positioned above the gate region, acts as a mediator that reduces the direct electromagnetic coupling between source and drain metallization layers, thereby decreasing parasitic capacitance while maintaining necessary electrical connections
2Productivity
If device dimensions are reduced to improve integration density, then more devices can be packed into smaller areas, but coupling between terminals increases due to reduced spacing
Solution Approach 1:
The shielding structure serves as a mediator that enables closer spacing of source and drain terminals without increasing parasitic coupling. By positioning the shielding structure above the gate region, the patent allows for reduced device footprint and improved integration density while the shielding structure maintains electrical isolation between adjacent terminals
3Area of stationary object
If source and drain contacts are positioned close to the gate to reduce device area, then device footprint is reduced, but capacitance between contacts and gate increases
Solution Approach 1:
The shielding structure positioned above the gate region acts as an intermediary that reduces the capacitive coupling between source/drain contacts and the gate. This shielding structure provides electromagnetic shielding that allows contacts to be positioned closer to the gate for reduced device footprint while maintaining low parasitic capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The shielding structure effectively decreases parasitic capacitances, enhancing switching times and enabling the use of MOS devices in low-power applications with improved input bandwidth and noise rejection, particularly in amplifiers and power supply circuits.
Implementation Method 1
The proximity of the source contact 110 and the drain contact 120 to the gate 108 establishes a respective source contact-gate capacitance 130 and a drain contact-gate capacitance 132
Data Source
AI summary
Mutual capacitances between regions of a MOS device become substantial factors that limit the speed and performance of the device as the device dimensions are reduced in size. A MOS transistor with a shielding structure formed above the gate is described. The shielding structure is connected to ground and is configured to reduce at least some of these mutual capacitances.