Metal Gate Line Cutting via Segmented Etching
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Solution Overview
Problem
Existing methods for fabricating IC devices face challenges in cutting metal gate electrode lines into sub-electrode lines, particularly as device scaling down increases complexity and reduces feature sizes, leading to constrained etching processes.
Innovation Solution
A method involving the formation of a combination of first and second gate metal layers, with subsequent etching processes to cut the metal gate line into sub-lines, utilizing sacrificial layers and patterned hard masks to relax etching constraints and allow for thinner metal layers, enabling more precise control and flexibility in metal etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If metal gate electrode lines are cut into sub-electrode lines using conventional etching methods, then the metal gate can be formed, but the etching process becomes constrained and difficult as device scaling down reduces feature sizes
Solution Approach 1:
The patent divides the metal gate line cutting process into multiple sequential etching steps, where each step creates a portion of the final sub-electrode line pattern. This segmentation allows each individual etching step to operate at relaxed dimensions while collectively achieving the final scaled-down feature size, thereby maintaining manufacturing precision without overwhelming etching process complexity
Solution Approach 2:
The patent introduces a vertical dimension by forming the metal gate structure in multiple stacked layers (first metal gate layer, second metal gate layer, third metal gate layer). The line cuts are performed at different vertical levels and depths, transforming a two-dimensional planar cutting problem into a three-dimensional multi-level structure that resolves the constraints of conventional single-plane etching
2Productivity
If device scaling down increases functional density, then production efficiency improves and costs lower, but the complexity of processing and manufacturing increases
Solution Approach 1:
The patent segments the metal gate formation and cutting operations into multiple discrete steps with intermediate structures (such as sacrificial layers and spacer formations). This segmentation allows each step to be optimized independently for manufacturing efficiency while the cumulative effect achieves the scaled-down device dimensions, thereby improving productivity without proportionally increasing overall processing complexity
Solution Approach 2:
The patent performs preliminary actions by forming sacrificial layers and spacers before the final metal gate line cutting. These preliminary structures pre-define the eventual cut patterns and provide self-aligned references for subsequent etching steps, reducing the need for complex alignment procedures and simplifying the overall manufacturing process despite device scaling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the successful formation and cutting of metal gate lines in semiconductor devices, even at smaller scales, by employing a two-step etching process that reduces metal layer thickness and relaxes etching constraints, improving processing efficiency and device performance.
Implementation Method 1
subsequent etching processes to cut the metal gate line into sub-lines
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a first fin and a second fin on a substrate, forming a first metal-gate line over a first and a second gate regions, applying a first line-cut to separate the first metal-gate line into a first sub-metal gate line and a second sub-metal gate line and forming a second metal-gate line over the first sub-metal gate line and the second sub-metal gate line, applying a second line-cut to separate the second metal-gate line into a third sub-metal gate line and a fourth sub-metal gate line such that a gap is formed between the third sub-metal gate line and the fourth sub-metal gate line and forming an isolation region within the gap.