Quantized Metal Contacts for Low-Resistance Semiconductor Interfaces
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Solution Overview
Problem
As integrated circuit devices shrink, the contact resistance between metal and semiconductor interfaces increases due to mismatched Fermi levels and bandgap pinning, leading to higher parasitic resistance, which existing solutions like reactive contacts and bandgap modifications have not adequately addressed.
Innovation Solution
The implementation of a graded metal/semiconductor interface using low-density-of-states metals like antimony and bismuth, which are more confined towards the semiconductor, reducing contact resistance by breaking down the barrier height into sub-components and using dielectric materials to further confine the metal, thereby smoothing out band discontinuities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal is deposited onto semiconductor material to form contacts, then electrical connection is established, but contact resistance increases due to Fermi level pinning and bandgap mismatch
Solution Approach 1:
The patent introduces an intermediary layer with graded bandgap between the metal contact and the semiconductor material. This intermediate layer has a bandgap that transitions from matching the metal's bandgap at the contact interface to matching the semiconductor's bandgap at the semiconductor interface, thereby mediating the Fermi level alignment and reducing contact resistance caused by bandgap mismatch and Fermi level pinning.
Solution Approach 2:
The patent changes the bandgap parameter of the intermediate layer by creating a graded structure where the bandgap varies continuously from the metal interface to the semiconductor interface. This parameter change allows the intermediate layer to adapt to both the metal and semiconductor bandgaps, reducing the abrupt discontinuity that causes high contact resistance.
2Volume of moving object
If contact area is reduced to scale down integrated circuit devices, then device size decreases, but contact resistance increases proportionally
Solution Approach 1:
The patent changes the electrical parameters of the contact structure by introducing an intermediate layer with optimized bandgap properties. This allows maintaining low contact resistance even when the contact area is reduced for scaling, as the graded bandgap structure improves carrier transport efficiency across the contact interface.
Solution Approach 2:
The patent creates a composite contact structure consisting of multiple layers with different bandgap materials. The intermediate layer is composed of materials with bandgaps that bridge the gap between metal and semiconductor, forming a composite structure that optimizes both electrical performance and dimensional scaling.
3Reliability
If reactive metal contacts are used to improve electrical connection, then contact resistance decreases, but interface instability and oxidation increase
Solution Approach 1:
The patent employs a composite intermediate layer structure that combines materials with appropriate bandgap properties and chemical stability. This composite structure provides both low contact resistance through optimized band alignment and interface stability through the use of materials resistant to oxidation and chemical degradation.
Solution Approach 2:
The intermediate layer acts as a protective intermediary between the metal contact and semiconductor, reducing the reactivity at the interface. This mediator layer prevents direct interaction between reactive metal and semiconductor surfaces, thereby stabilizing the interface composition while maintaining low contact resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces contact resistance by exponentially decreasing the barrier height, improving the overall performance of transistor devices by minimizing parasitic resistance.
Implementation Method 1
grading a metal/semiconductor material interface to smooth out a band discontinuity
Implementation Method 2
the Fermi level of the metal and semiconductor material do not match. The result is a pinning of the Fermi level in a semiconductor to a particular level
Implementation Method 3
confining (e.g., quantizing) a low density of states metal with the metal being more confined (e.g., more quantized) toward the semiconductor
Implementation Method 4
reducing contact resistance by breaking down the barrier height into sub-components
Data Source
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AI summary
An apparatus including an integrated circuit device including at least one low density of state metal/semiconductor material interface, wherein the at least one low density of state metal is quantized. An apparatus including an integrated circuit device including at least one interface of a low density of state metal and a semiconductor material, wherein a contact area of the metal at the interface is graded. A method including confining a contact area of a semiconductor material; and forming a metal contact in the contact area.