FinFET Sense Amplifier Layout With Uniform Gate Lengths

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Solution Overview

Problem

In semiconductor fabrication, sense amplifiers in memory chips face device mismatch issues due to varying poly gate lengths and oxide definition regions, leading to increased layout area and potential incorrect data reads.

Innovation Solution

Implementing FinFET technology with uniform poly gate lengths for all NMOS devices in a sense amplifier, allowing them to share a common oxide definition region, which reduces device mismatch and layout size by eliminating the need for separate oxide definition regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If different poly gate lengths are used for NMOS devices in the sense amplifier, then device functionality is achieved, but device mismatch increases and layout area expands

Engineering Contradiction:
Improvedevice mismatchVSAvoidlayout area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the gate length parameter from variable to uniform across all NMOS devices. Specifically, all NMOS devices (including sensing devices N0, N1 and enabling device N2) are designed with the same poly gate length Lg, which eliminates device mismatch caused by parameter variation and allows them to share a common oxide definition region, thereby reducing layout area.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If uniform poly gate length is used for all NMOS devices, then device mismatch is reduced and layout area is minimized, but device complexity in design is increased

Engineering Contradiction:
Improvedevice mismatchVSAvoiddesign complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges previously separate oxide definition regions into a single common oxide definition region. By making all NMOS devices have uniform gate lengths, the patent combines the oxide definition regions that were previously needed for different gate length devices, simplifying the overall design and reducing manufacturing complexity while improving device matching.

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If NMOS devices are placed in separate oxide definition regions, then device functionality is maintained, but sensing precision of differential signals deteriorates

Engineering Contradiction:
Improvedifferential signal sensingVSAvoidoxide definition region structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies homogeneity by ensuring all NMOS devices within the common oxide definition region have identical poly gate lengths. This uniformity creates homogeneous electrical characteristics across devices, which improves differential signal sensing precision by reducing threshold voltage mismatches and enabling more accurate signal discrimination.

Inventive Principle:
Principle #33Homogeneity

Data Source

PatentUS20150015335A1Sense amplifier layout for finfet technology
Publication Date: 2015.01.15 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20150015335A1 patent drawing
  • US20150015335A1 patent drawing
  • US20150015335A1 patent drawing

AI summary

A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.