Sacrificial Spacer Gate Isolation for CMOS Metal Silicide
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Solution Overview
Problem
The self-aligned process for forming Ni or Ni—Pt silicide in CMOS devices leads to lateral diffusion of metal, affecting device performance due to reduced dimensions, resulting in gate leakage current and reliability issues.
Innovation Solution
The method involves forming sacrificial spacers on the sidewalls of the gate region before depositing the metal layer, which is then removed after the metal layer reacts with the semiconductor region to form a metal-semiconductor compound, thereby reducing lateral diffusion by creating a distance between the metal layer and the gate/channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Ni or Ni—Pt is used to form metal-semiconductor compound by self-aligned process, then contact resistance is reduced, but lateral diffusion occurs affecting device performance
Solution Approach 1:
The patent applies preliminary action by forming sacrificial spacers on the gate sidewalls before depositing the metal layer. These spacers pre-establish a physical barrier that prevents lateral diffusion of Ni or Ni—Pt into the channel region during subsequent annealing, thus resolving the contradiction between achieving low contact resistance and maintaining precise device dimensions
Solution Approach 2:
The sacrificial spacers act as an intermediary element between the metal layer and the gate/channel region. This intermediary structure temporarily occupies the space that would otherwise be invaded by laterally diffusing metal, allowing the metal-semiconductor compound formation to proceed with controlled boundaries that prevent harmful diffusion while maintaining low contact resistance
2Reliability
If metal layer is deposited close to gate region, then contact resistance is lowered, but metal diffuses to channel region causing gate leakage
Solution Approach 1:
The sacrificial spacers are formed in advance on the gate sidewalls before metal deposition, pre-establishing a protective barrier that prevents metal atoms from reaching the channel region during diffusion, thus eliminating gate leakage current while allowing the metal layer to be positioned optimally for low contact resistance
Solution Approach 2:
The patent converts the potentially harmful lateral diffusion of metal into a beneficial controlled reaction. By using sacrificial spacers, the metal diffusion is directed to react with the semiconductor region to form low-resistance compound while the spacer barrier simultaneously prevents diffusion into the channel, transforming what would be a harmful effect into a useful one
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces metal layer diffusion to the channel and gate regions, improving device performance by maintaining the integrity of device dimensions and reducing contact resistance.
Implementation Method 1
performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region
Implementation Method 2
Due to easily diffusing of Ni and Ni—Pt, lateral diffusion of Ni or Ni—Pt occurs in the self-aligned process
Data Source
AI summary
A method for manufacturing a semiconductor device is disclosed, comprising: providing a substrate, a gate region on the substrate and a semiconductor region at both sides of the gate region; forming sacrificial spacers, which cover a portion of the semiconductor region, on sidewalls of the gate region; forming a metal layer on a portion of the semiconductor region outside the sacrificial spacers and on the gate region; removing the sacrificial spacers; performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region; and removing unreacted metal layer. By separating the metal layer from the channel and the gate region of the device with the thickness of the sacrificial spacers, the effect of metal layer diffusion on the channel and the gate region is reduced and performance of the device is improved.