Source-Coupled Cap Structure for HEMT Saturation Current Control
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Solution Overview
Problem
High voltage transistor devices, such as HEMT devices, face device failure due to excessive saturation current during high voltage applications, leading to local heating and reliability issues.
Innovation Solution
A cap structure made of the same material as the gate electrode is introduced, laterally positioned between the gate and source contacts, and biased with the source contact to partially deplete the channel region, reducing saturation current and mitigating device failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If HEMT device operates at high voltage, then power handling capability is improved, but saturation current becomes excessive causing device failure
Solution Approach 1:
The gate structure is segmented into two distinct parts: a conventional gate electrode and a separate cap structure. This segmentation allows independent control of the gate voltage and cap voltage, enabling the cap to specifically target and reduce saturation current while the gate maintains overall device operation. The cap structure acts as an independent control element that can be biased separately to deplete the channel and reduce saturation current.
Solution Approach 2:
The cap structure serves as an intermediary element between the gate electrode and the channel region. By positioning the cap laterally between the gate and source contact and allowing it to extend over the channel, it mediates the electrical field distribution and provides an additional degree of control over carrier flow. The cap structure translates gate bias into localized channel depletion, effectively reducing saturation current.
2Reliability
If saturation current is reduced to prevent device failure, then reliability is improved, but power handling capability may be compromised
Solution Approach 1:
The device operates dynamically with two independent voltage controls: gate voltage for overall device operation and cap voltage for saturation current suppression. By applying appropriate bias conditions (e.g., negative cap voltage relative to source), the device can dynamically adjust the depletion level in the channel, achieving low saturation current while maintaining adequate power handling capability through proper gate voltage selection.
Solution Approach 2:
The invention changes the electrical parameters by introducing a separate cap voltage parameter independent of the gate voltage. This additional parameter allows independent optimization of saturation current reduction and power handling capability. By adjusting the cap voltage, the depletion width and saturation current can be controlled without directly affecting the gate-driven current flow, enabling simultaneous achievement of both reliability and power handling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The cap structure reduces saturation current by up to 60% and increases the HEMT device's ability to withstand high voltage biases without breakdown, enhancing reliability during high voltage applications.
Implementation Method 1
the cap structure is biased according to the source contact and puts the channel region into a partially depleted mode
Data Source
AI summary
In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer disposed over a base substrate, and an active layer disposed on the channel layer. A source contact and a drain contact are over the active layer and are laterally spaced apart from one another along a first direction. A gate electrode is arranged on the active layer between the source contact and the drain contact. A passivation layer is arranged on the active layer and laterally surrounds the source contact, the drain contact, and the gate electrode. A conductive structure is electrically coupled to the source contact and is disposed laterally between the gate electrode and the source contact. The conductive structure extends along an upper surface and a sidewall of the passivation layer.