FinFET DMUX Circuit Segmentation for Area and Power Reduction
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Solution Overview
Problem
Existing DMUX circuits face challenges in reducing area-cost and improving performance, with traditional designs often requiring high transistor counts and consuming more power while being slower.
Innovation Solution
The implementation of DMUX circuits using FinFET architecture and innovative logic circuits without transmission gates, which reduce transistor counts and optimize layout structures to minimize area usage and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional DMUX circuit designs are used, then the circuit can perform basic multiplexing function, but the transistor count is high and area usage is large
Solution Approach 1:
The DMUX circuit is segmented into multiple independent logic units, each handling a specific data input channel. Each unit consists of dedicated AND gates and OR gates that process one data input independently. This segmentation allows for optimized transistor usage in each segment while maintaining the overall multiplexing function, thereby reducing the total transistor count and area usage compared to a monolithic design.
Solution Approach 2:
The invention changes the logical parameters of the circuit by implementing the multiplexing function using a combination of AND-OR logic instead of traditional transmission gate-based designs. This parameter change in the logical implementation approach enables more efficient transistor utilization and reduces the overall transistor count while maintaining the same multiplexing functionality.
2Use of energy by moving object
If traditional DMUX circuit designs are used, then the circuit can perform multiplexing, but power consumption is high
Solution Approach 1:
By segmenting the circuit into independent logic units that process each data channel separately, the invention enables more efficient power management. Each segment can be optimized to minimize switching activity and power consumption, and the modular structure allows for better control of power distribution across different input channels, thereby reducing overall power consumption.
Solution Approach 2:
Changing the implementation approach from transmission gates to AND-OR logic fundamentally alters the power consumption characteristics. The AND-OR logic structure reduces leakage current and dynamic power consumption by minimizing the number of simultaneous switching elements and reducing the overall transistor count, leading to lower power consumption for the same multiplexing function.
3Speed
If traditional DMUX circuit designs are used, then the circuit can perform multiplexing, but speed is slow
Solution Approach 1:
Segmenting the multiplexing function into separate logic units for each data input channel allows for optimized signal paths in each segment. This segmentation reduces the critical path delay by preventing signal contention and reducing the number of sequential logic stages that signals must traverse, thereby increasing the overall operating speed of the multiplexer.
Solution Approach 2:
The parameter change from transmission gate-based logic to AND-OR logic improves speed by reducing the propagation delay through the logic gates. The AND-OR structure provides more direct signal paths with fewer switching elements in the critical path, enabling faster signal transmission from input to output while maintaining the multiplexing function.
Data Source
AI summary
A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.