FinFET Fabrication Using Dual Mask Segmentation for Fin Quality

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Solution Overview

Problem

Conventional FinFET fabrication techniques face challenges in maintaining fin structure quality and stability due to complex mask patterns and photolithography limitations, leading to issues like corner rounding and inconsistent fin lengths, which affect device performance.

Innovation Solution

The use of two mask layers in the FinFET fabrication process, where a first mask layer with precise openings is used to remove fin structures in one region while protecting those in another, and a second mask layer ensures the integrity of the fin structures by covering and exposing them appropriately for etching, thereby simplifying the double patterning process and improving pattern quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional single mask layer photolithography is used to form fin structures, then the fabrication process is simple, but the fin structure quality deteriorates due to corner rounding and inconsistent fin lengths

Engineering Contradiction:
Improvefabrication process simplicityVSAvoidfin structure quality
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent divides the single mask layer into two separate mask layers (first mask layer and second mask layer), each performing a specific function. The first mask layer defines the fin region boundaries, while the second mask layer defines the gate pattern. This segmentation allows each mask to be optimized for its specific purpose, preventing corner rounding and ensuring consistent fin lengths while maintaining process simplicity.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If complex mask patterns are used to improve fin structure precision, then manufacturing precision improves, but device complexity increases

Engineering Contradiction:
Improvefin structure precisionVSAvoidmask pattern complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The complex patterning task is segmented into two simpler mask layers. The first mask layer uses a relatively simple pattern to define the fin region, and the second mask layer uses another simple pattern to define the gate. This avoids the need for a single complex mask pattern, reducing device complexity while achieving high fin structure precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first mask layer performs a preliminary action by defining the fin region boundaries before the second mask layer is applied. This preliminary patterning simplifies the subsequent gate formation process, as the second mask only needs to define the gate pattern within the already-established fin region, rather than dealing with the full complexity of both patterns simultaneously.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If photolithography is used to form fin structures, then the process is straightforward, but fin structure stability deteriorates due to pattern inconsistencies

Engineering Contradiction:
Improveprocess straightforwardnessVSAvoidfin structure stability
Core Design Contradiction:
Ease of manufactureVSStability of the object's composition

Solution Approach 1:

The photolithography process is segmented into two distinct steps with two mask layers. The first mask layer establishes stable fin region boundaries, and the second mask layer adds the gate pattern. This segmentation ensures that each photolithography step works with a simpler, more stable pattern, reducing pattern inconsistencies and improving overall fin structure stability while keeping the process straightforward.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9142675B2Fin field effect transistors and fabrication method thereof
Publication Date: 2015.09.22 SEMICON MFG INT (BEIJING) CORP
  • US9142675B2 patent drawing
  • US9142675B2 patent drawing
  • US9142675B2 patent drawing

AI summary

A method is provided for fabricating a fin field-effect transistor. The method includes providing a substrate having a first region and a second region; and forming a plurality of fin structures on a surface of the substrate. The method also includes forming a first mask layer having a plurality of first openings exposing the fin structures in the first region near the second region; and removing the fin structures in the first region near the second region. Further, the method includes forming a second mask layer on the fin structures in the second region; and removing the fin structures in the first region. Further, the method also includes forming fins by etching the substrate using the fin structures in the second region as an etching mask; and forming a gate structure and source/drain regions in the fins at both sides of the gate structure.