FinFET Epitaxial Source/Drain Sequencing for Uniform Isolation
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Solution Overview
Problem
The existing methods for fabricating FinFET devices face challenges due to structural differences between n-type and p-type source/drain features, leading to poor feature uniformity and potential misalignment issues, as forming n-type source/drain features first reduces the processing window for subsequent fabrication of p-type features.
Innovation Solution
The method involves forming p-type source/drain features before n-type features in FinFET devices, which enlarges the processing window by recessing and epitaxially growing semiconductor materials on the fins, allowing for improved control and uniformity in the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If n-type source/drain features are formed first, then device performance is improved, but processing window is reduced and manufacturing precision deteriorates
Solution Approach 1:
The patent inverts the conventional formation sequence by forming p-type source/drain features first instead of n-type features first. This reversal of the process sequence resolves the contradiction by providing adequate processing window for both feature types while maintaining device performance requirements.
Solution Approach 2:
The patent performs preliminary actions by forming p-type source/drain features with their specific material and structural requirements before proceeding to n-type feature formation. This preliminary formation allows optimization of p-type features without compromising subsequent n-type feature uniformity.
2Reliability
If n-type source/drain features are formed first, then device performance is improved, but processing time is reduced, but alignment precision deteriorates
Solution Approach 1:
By inverting the formation sequence to form p-type features first, the patent ensures that both n-type and p-type features can be formed with proper alignment margins. The inverted sequence prevents cumulative alignment errors that would occur in the conventional sequence.
3Area of moving object
If feature size is decreased, then functional density is increased, but processing complexity increases
Solution Approach 1:
The patent applies preliminary actions by preparing and forming p-type source/drain features with their specific material layers and structures before n-type feature formation. This preliminary preparation simplifies subsequent processing steps despite reduced feature sizes by establishing a controlled foundation.
Solution Approach 2:
The patent segments the source/drain formation process into distinct sequential stages for p-type and n-type features, each with optimized processing conditions. This segmentation allows complex reduced-size feature formation to be managed through controlled, separate process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity and reduces misalignment risks in the fabrication of FinFET devices by expanding the processing window, improving the overall fabrication efficiency and quality of the semiconductor structure.
Implementation Method 1
epitaxially growing semiconductor materials on the fins
Data Source
AI summary
A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.