FinFET Source/Drain Epitaxy Layout for Selective Region Merging
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Solution Overview
Problem
Existing FinFET devices face challenges in selectively merging or separating source/drain epitaxy regions for different circuit types, such as logic and SRAM circuits, due to simultaneous epitaxy processing, which complicates manufacturing and increases costs.
Innovation Solution
The method involves forming fin spacers with adjustable heights in different device regions to control the merging or separation of epitaxy regions during the epitaxy process, allowing for flexible formation of merged or un-merged source/drain regions through precise etching and deposition techniques, enabling common deposition and epitaxy processes while meeting specific circuit requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If simultaneous epitaxy is performed for different regions to save manufacturing cost, then manufacturing cost is reduced, but it becomes difficult to selectively merge or separate epitaxy regions for different circuits
Solution Approach 1:
The patent applies local quality by forming fin spacers with different heights in different device regions. Specifically, first fin spacers are formed with a first height in a first device region, while second fin spacers are formed with a second height in a second device region. This allows the epitaxy regions to be merged in one region while remaining separate in another region, enabling circuit-specific customization without requiring separate epitaxy processes.
2Adaptability or versatility
If fin spacers with different heights are formed in different device regions, then selective merging or separation of epitaxy regions is enabled, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the device structure into distinct regions with different fin spacer configurations. First fin spacers are formed in a first device region with a first height, while second fin spacers are formed in a second device region with a second height. This segmentation allows independent control of epitaxy region merging behavior in different circuit types, enabling logic circuits to have merged regions while SRAM circuits maintain separate regions.
Solution Approach 2:
The patent applies parameter changes by varying the height parameter of fin spacers across different device regions. By controlling the fin spacer height, the patent directly influences whether epitaxy regions merge or remain separate during the epitaxy process. This parameter control enables flexible adaptation to different circuit requirements without changing the fundamental epitaxy process.
3Manufacturing precision
If separate epitaxy processes are used for different circuits to achieve precise control, then circuit-specific requirements are met, but manufacturing cost increases
Solution Approach 1:
The patent applies universality by using a single common epitaxy process that can serve multiple device regions with different requirements. The fin spacer height variation enables the same epitaxy process to produce merged regions in logic circuits and separate regions in SRAM circuits simultaneously. This multi-functional approach eliminates the need for separate epitaxy processes while maintaining precise control over region merging behavior.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by allowing flexible formation of epitaxy regions, enhancing the drive current of FinFETs with merged regions and compactness without requiring separate epitaxy processes for different circuits, thus addressing the complexity and cost issues in existing FinFET fabrication.
Implementation Method 1
an epitaxy process is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses
Data Source
AI summary
A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.