FinFET ESD Protection via Impurity Compensation in Punch-Through Stopper
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Solution Overview
Problem
Conventional ESD protection methods are not suitable for FinFET construction due to narrowing fins, which increases the risk of electrical overstress and damage to semiconductor devices, necessitating a compatible ESD protection device and fabrication method.
Innovation Solution
The method involves forming doped regions with specific impurity concentrations in fins of a semiconductor device, including a punch-through stopper and additional doped regions to induce punch-through currents, providing current leakage paths for ESD protection, while being fully compatible with the FinFET process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional ESD protection methods are used, then ESD protection is provided, but the methods are not suitable for FinFET construction with narrowing fins
Solution Approach 1:
The patent modifies the impurity concentration parameters in the fin structure to enable ESD protection functionality. Specifically, it creates a punch-through stopper with higher impurity concentration than the substrate, and implants additional impurities into the PTS and source/drain regions to compensate impurity concentrations, thereby transforming the fin structure into an ESD protection device compatible with FinFET process
2Reliability
If a punch-through stopper is formed with higher impurity concentration, then the PTS can induce punch-through currents for ESD protection, but the impurity concentration needs compensation to control electrical characteristics
Solution Approach 1:
The patent performs preliminary impurity compensation by implanting impurities into the punch-through stopper and source/drain regions before final device operation. This preliminary action of compensating impurity concentrations ensures that the PTS can induce punch-through currents effectively while maintaining controlled electrical characteristics, resolving the contradiction between ESD protection capability and device complexity
Solution Approach 2:
The patent applies local quality by creating regions with different impurity concentrations at specific locations. The punch-through stopper has higher impurity concentration than the substrate, and additional impurity compensation is applied locally to the PTS and source/drain regions, enabling localized control of electrical characteristics to facilitate punch-through current induction while maintaining overall device functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances ESD performance by facilitating current leakage and discharge, effectively protecting internal circuits and simplifying the fabrication process within the existing FinFET framework.
Implementation Method 1
A first impurity of the second conductivity type is implanted into the PTS, so as to compensate the impurity concentration of the PTS. An impurity of the first conductivity type is implanted into a bottom part of the source and drain regions, so as to compensate an impurity concentration of the bottom part of the source and drain regions.
Data Source
AI summary
A method for fabricating a semiconductor device is provided. A fin of a first conductivity type is formed on a substrate of the first conductivity type. A gate is formed on the substrate, wherein the gate covers a portion of the fin. Source and drain regions of a second conductivity type are formed in the fin at respective sides of the gate. A punch-through stopper (PTS) of the first conductivity type is formed in the fin underlying the gate and between the source and drain regions, wherein the PTS has an impurity concentration higher than that of the substrate. A first impurity of the second conductivity type is implanted into the PTS, so as to compensate the impurity concentration of the PTS.