FinFET ESD Protection via Segmented Doping and Gate Control
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Solution Overview
Problem
Fin-type field effect transistor (FinFET) devices require an effective electrostatic discharge (ESD) protection structure for high voltage applications, as the small-size fin generates insufficient hot carriers to trigger conventional GGNMOS transistors, necessitating a novel ESD protection solution.
Innovation Solution
A substrate structure with semiconductor fins and doped regions of different conductivity types, along with highly doped regions and gate structures, is used to create an ESD protection device that can effectively manage high voltage electrostatic discharges by connecting the highly doped regions to power supply or ground potentials, and includes a signal input terminal for external signal reception.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional GGNMOS transistors are used for ESD protection in FinFET devices, then the structure is simple and manufacturing is easy, but the hot carrier generation is insufficient due to small-size fins, making the protection ineffective
Solution Approach 1:
The ESD protection device is segmented into multiple functional regions: a first doped region with first conductivity type, a second doped region with second conductivity type, highly doped regions for charge injection, and gate structures for control. This segmentation allows each region to perform its specific function optimally, ensuring effective ESD protection while maintaining manufacturability through standardized FinFET fabrication processes
Solution Approach 2:
Different regions of the ESD protection device are doped with different dopant concentrations and conductivity types to create localized functional zones. The highly doped regions provide efficient charge injection, while the lightly doped regions provide appropriate electric field distribution. This local quality optimization ensures effective hot carrier generation in the specific region where it is needed for ESD protection
2Productivity
If the fin size is reduced to maintain scalability in FinFET devices, then device integration density increases, but the amount of generated hot carriers becomes insufficient to effectively trigger ESD protection
Solution Approach 1:
The invention changes the doping parameters by introducing highly doped regions with dopant concentrations significantly higher than the surrounding doped regions. This parameter change enables efficient charge injection and hot carrier generation even in small-size fins, maintaining ESD protection effectiveness while allowing continued scaling for high integration density
Solution Approach 2:
The ESD protection device uses composite doping structures combining regions of different conductivity types (first and second conductivity types) with different dopant concentrations. This composite structure creates optimal conditions for hot carrier generation in scaled FinFET devices, enabling effective ESD protection without compromising integration density
3Reliability
If highly doped regions are added to enhance hot carrier generation, then ESD protection effectiveness improves, but manufacturing precision requirements increase
Solution Approach 1:
The highly doped regions are formed as part of the preliminary device structure before final ESD protection activation. The doping profiles and regions are established during standard FinFET manufacturing steps, ensuring precise dopant placement and concentration control is built into the fabrication process itself rather than requiring additional precision steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed ESD protection structure effectively prevents electrostatic discharges from affecting internal circuits by redirecting excess charges through the doped regions, providing reliable protection for FinFET devices in high voltage applications.
Implementation Method 1
The proposed ESD protection structure effectively prevents electrostatic discharges from affecting internal circuits by redirecting excess charges through the doped regions
Data Source
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AI summary
An ESD protection device includes a semiconductor substrate, first and second fins, first and second doped regions adjacent to each other and having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin. The second doped region includes a second portion of the substrate and a second region of the first fin. The device also includes a first gate structure on a portion of first and second regions of the first fin, a first highly doped region in the first region of the first fin and having a same conductivity type as the first doped region, and a dopant concentration higher than the first doped region, and a second highly doped region in the second fin and having a same conductivity type as the second doped region, and a dopant concentration higher than the second doped region.