FinFET Structure With Extended Current Path For High Voltage And Speed
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Solution Overview
Problem
Conventional semiconductor manufacturing processes cannot produce finFETs that simultaneously operate at high speeds and high voltages, failing to meet the needs of integrated circuit designs requiring both low and high operating voltage transistors in a single device.
Innovation Solution
The development of finFET structures with an extended current path between source and drain terminals, allowing them to interface with high voltage signals while maintaining high switching speeds, fabricated using existing CMOS finFET processing methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional FET device scaling is performed to achieve higher operating speeds, then switching speed is improved, but operating voltage must be reduced due to thinner gate dielectric layer requirements
Solution Approach 1:
The patent transitions from a planar FET structure to a vertically-oriented finFET structure. The fin extends vertically from the substrate, allowing the gate to wrap around three sides of the fin (front, left, and right sides). This vertical dimension enables enhanced gate control over the channel while maintaining a physically larger device footprint, thus achieving high switching speed without requiring reduced operating voltage.
Solution Approach 2:
The patent employs a composite structure combining the vertical fin (typically silicon) with a wrapped gate structure that includes gate dielectric and gate electrode layers. This composite architecture allows the gate to control the channel from multiple directions (front, left, and right sides), providing superior electrical characteristics and enabling the device to operate at both high speed and high voltage simultaneously.
2Reliability
If conventional finFET structure is used with wrapped gate, then gate control is improved, but device cannot simultaneously achieve high speed and high operating voltage characteristics
Solution Approach 1:
The patent extends the gate wrapping to include not only the front and side surfaces but also introduces rear gate coverage in advanced embodiments. This multi-dimensional gate arrangement (front, sides, and rear) provides comprehensive channel control, enabling the finFET to maintain excellent gate control while being adaptable to both high-speed and high-voltage operating conditions.
Solution Approach 2:
The patent designs the finFET structure to be universally applicable across different operating voltage requirements. By optimizing the fin dimensions, gate wrapping configuration, and doping profiles, the same basic structure can be tuned to achieve either high-speed or high-voltage characteristics, making it versatile for various integrated circuit applications without requiring fundamentally different device architectures.
3Ease of manufacture
If planar FET structure is used, then manufacturing is simpler, but device density and switching speed are limited
Solution Approach 1:
The patent adopts a vertically-oriented fin structure that extends upward from the substrate rather than relying solely on planar geometry. This vertical dimension increases the effective channel area and improves gate control without significantly complicating the manufacturing process, as the fin can be formed using standard epitaxial growth or selective oxidation techniques followed by conventional patterning and doping steps.
Data Source
AI summary
A field effect transistor (FET) having one or more fins provides an extended current path as compared to conventional finFETs. A raised source terminal is disposed on a fin adjacent to a sidewall spacer of a gate structure. The drain terminal and a first portion of the gate structure overlie a first well of a first conductivity type. A raised drain terminal is disposed such that it is spaced apart from the gate structure sidewalls. In some embodiments the drain terminal is disposed on a second, separate fin. the drain terminal and a second portion of the gate structure overlie a second well of a second conductivity type.