Three-Sided Field Plating in FinFET Drift Regions
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Solution Overview
Problem
Fin field effect transistors (FinFETs) require enhanced designs to increase drain breakdown voltage and reduce leakage current, as existing technologies do not effectively utilize field plating on non-planar structures to achieve these goals.
Innovation Solution
The implementation of field plating on three sides of the fin, specifically the drift region, in FinFETs, using a thicker field plating oxide layer than the gate oxide layer, to enhance breakdown voltage and reduce leakage current, involves a method that includes forming a fin on a semiconductor substrate, depositing a dielectric layer, etching to create the field plating oxide, and forming a gate oxide layer on the body region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If field plating is applied to planar transistors, then drain breakdown voltage is increased and leakage current is reduced, but FinFETs with non-planar structures do not effectively utilize field plating
Solution Approach 1:
The patent extends field plating from traditional planar surfaces to three-dimensional FinFET structures by forming the field plating oxide layer on multiple sides (first side, second side, and third side) of the drift region. This dimensional extension allows the field plating to effectively cover the non-planar fin structure, increasing drain breakdown voltage and reducing leakage current in vertical-channel devices.
Solution Approach 2:
The field plating oxide layer is selectively formed only on specific sides of the drift region (first side, second side, and third side) rather than uniformly across the entire structure. This localized application targets the specific regions where field enhancement is most needed in the FinFET architecture, optimizing breakdown voltage without unnecessarily increasing overall device complexity.
2Reliability
If field plating oxide layer is made thicker than gate oxide layer, then breakdown voltage is enhanced, but device area and complexity increase
Solution Approach 1:
The patent employs different oxide layer thicknesses in different regions: the field plating oxide layer is made thicker than the gate oxide layer specifically in the drift region where high voltage breakdown is needed, while the gate oxide layer remains thinner for optimal gate control. This localized thickness differentiation enhances breakdown voltage without uniformly increasing device complexity across the entire structure.
Data Source
AI summary
An integrated circuit (IC) having a fin field effect transistor (FinFET) includes a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, a drift region, and field plating oxide layer. The drift region is adjacent the drain region. The field plating oxide layer is on a first side, a second side, and a third side of the drift region.