FinFET Fin Length Segmentation for SRAM Write Stability
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Solution Overview
Problem
The conflicting requirements of strong logic and weak SiGe pFETs in FinFET technology pose a challenge in achieving a sufficient Id ratio for SRAM applications, where the SiGe pFET needs to be weak to prevent write failure.
Innovation Solution
The solution involves forming logic finFET devices with longer SiGe fins under higher strain and SRAM pull-up finFET devices with shorter SiGe fins under relaxed strain, using selective cutting of fin structures and appropriate gate formation to achieve the desired Id ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If SiGe pFET is made strong for logic applications, then logic performance is improved, but SRAM write capability deteriorates due to insufficient gamma ratio
Solution Approach 1:
The patent applies local quality by creating different fin length configurations for different device types within the same semiconductor structure. Logic finFETs have longer fins to maintain strong drive current, while SRAM pull-up finFETs have shorter fins to provide weak drive current for adequate gamma ratio. This spatial differentiation of structural parameters enables each device type to be optimized for its specific function without compromising the other.
2Speed
If SiGe pFET drive current is increased, then logic speed is improved, but SRAM cell stability deteriorates due to reduced gamma ratio
Solution Approach 1:
The invention implements local quality by varying the fin length parameter specifically for SRAM pull-up transistors compared to logic transistors. The shorter fins in SRAM devices locally reduce the drive current and strengthen the pull-up capability, ensuring adequate gamma ratio for stable write operations and preventing write failure, while logic devices maintain longer fins for high-speed operation.
3Ease of manufacture
If uniform fin length is used for all finFET devices, then manufacturing is simplified, but device performance optimization deteriorates due to inability to differentiate logic and SRAM characteristics
Solution Approach 1:
The patent applies segmentation by dividing the fin structures into different length categories based on device type requirements. Rather than using a uniform fin length for all devices, the methodology segments fins into longer fins for logic applications and shorter fins for SRAM applications. This segmentation enables differentiated performance optimization while maintaining compatibility with standard FinFET fabrication processes.
Solution Approach 2:
The invention implements local quality by creating spatial variations in fin length across the semiconductor device array. Each local region is configured with fin dimensions appropriate for its intended function - logic regions receive longer fins for high drive current, while SRAM regions receive shorter fins for adequate gamma ratio. This localized structural differentiation achieves both manufacturing feasibility and device-specific performance optimization.
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to segmented or cut finFET structures and methods of manufacture. The structure includes at least one logic finFET device having a fin of a first length, and at least one memory finFET device having a fin of a second length. The second length is shorter than the first length.