FinFET Fin Pitch and Width Control via Self-Aligned Quadruple Patterning

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current semiconductor devices face challenges in scaling density and improving operation performance, particularly in suppressing short channel effects and maintaining fin width consistency due to loading effects during fabrication.

Innovation Solution

The semiconductor device features a substrate with fin groups arranged in specific pitches and orientations, using a self-aligned quadruple patterning process to form fins with consistent widths and pitches, reducing the loading effect and enhancing operation performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional patterning processes are used to form fins, then fabrication is simpler, but loading effects cause critical dimension increases and fin width inconsistency

Engineering Contradiction:
Improvefin width consistencyVSAvoidpatterning process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patterning process is divided into multiple discrete steps (mandrel formation, spacer deposition, etching, mandrel removal, repetition) to achieve precise fin width control. This segmentation allows each step to be optimized independently, preventing loading effects from causing dimension variations while maintaining manufacturing precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Mandrel patterns are formed in advance as templates before the actual fin structures are created. These preliminary mandrels guide the subsequent spacer formation and etching processes, ensuring that fin widths are predetermined and consistent before the loading effects of final patterning occur.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If fin pitch is reduced to increase density, then device density improves, but short channel effects worsen

Engineering Contradiction:
Improvedevice densityVSAvoidshort channel effect suppression
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from planar fin structures to three-dimensional multi-gate FinFET structures. By adding vertical gates that wrap around the fin, control over the channel is extended into the vertical dimension, enabling effective short channel effect suppression even when horizontal fin pitch is reduced to increase device density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The gate structure acts as an intermediary that mediates between the source and drain regions, providing enhanced electrostatic control over the channel. This intermediate gate element allows the device to maintain reliability by suppressing short channel effects while operating at reduced fin pitches for higher density.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If multi-gate FinFET structure is implemented, then short channel effect suppression improves, but fabrication complexity increases

Engineering Contradiction:
Improveshort channel effect suppressionVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The self-aligned quadruple patterning process uses previously formed structures (mandrels, spacers) to automatically define the positions of subsequent features without requiring additional alignment steps. This self-service approach enables the complex multi-gate FinFET structure to be fabricated through self-organizing processes, reducing the practical complexity despite the advanced structure.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The fabrication process embeds multiple levels of pattern formation within each other, where spacers are formed around mandrels, then mandrels are removed and the process repeats. This nested sequence of operations efficiently creates the complex multi-gate structure by nesting fabrication steps within one another, managing structural complexity through process integration.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS11670636B2Method for fabricating semiconductor device
Publication Date: 2023.06.06 SAMSUNG ELECTRONICS CO LTD
  • US11670636B2 patent drawing
  • US11670636B2 patent drawing
  • US11670636B2 patent drawing

AI summary

A semiconductor device includes a substrate having first and second regions, first fin groups spaced along a first direction on the first region, each of the first fin groups including adjacent first and second fins having longitudinal directions in a second direction intersecting the first direction, and third to fifth fins spaced along a third direction on the second region, the third to fifth fins having longitudinal directions in a fourth direction intersecting the third direction. The third through fifth fins are at a first pitch, the first and second fins are at a second pitch equal to or smaller than the first pitch, each of the first fin groups is at a first group pitch greater than three times the first pitch and smaller than four times the first pitch, and a width of the first and second fins is same as width of the third fin.